jpeyron

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Everything posted by jpeyron

  1. jpeyron

    Using PMOD Connector for JTAG signals

    Hi @Vishwanath, I don't have access to the JTAG standard but it looks like the Pmod LVLSHFT could potentially help. If you can be more specific of what metrics you're looking for. i.e voltage, frequency. I could better respond if any of the Pmod Ports would work for your project. thank you, Jon
  2. jpeyron

    OS overhead of the JTAG-USB bits transfer

    Hi @jli853, I reached out to one of our design engineers about this forum thread. They responded that "Unless you do a non-blocking (overlapped) transfer the time it takes to execute the function will include not only the time to transfer the data over USB but also to shift it onto the JTAG scan chain. When the function returns all data has been transferred to the target JTAG device. How long that takes is going to very with the TCK frequency, as well as the PC side hardware and operating system. I don’t have any measured data to provide." thank you, Jon
  3. Hi @adjekovic, Could you attach your code for configuring the Pmod BT2? Have you added delays in between the commands? Here is a forum that that discusses this. thank you, Jon
  4. jpeyron

    Sample rate for Analog Discovery 2 with MATLAB

    Hi @Junfei Li, I've moved your thread to a section where a more AD2/WaveForms experience engineers look. cheers, Jon
  5. Hi @Abdul Qayyum, Here is a more advanced user guide that should help you with configuring the Pmod BT2. thank you, Jon
  6. Hi @adjekovic, Here is a more advanced users manual. I would look at page 8. A quick check to confirm that you are in command mode is to type x <cr> command after entering command mode. This command shows the a summary of the module’s current settings, such as the Bluetooth name, device class, and serial port settings. Make sue that you are returning to data mode, type ----<cr> or reset the module and re-connect. thank you, Jon
  7. jpeyron

    PmodAD5 evaluation

    Hi @Yacov Cohen, We have responded to your other post here. thank you, Jon
  8. Hi @Yacov Cohen, We are working on a fix for this code. We are hoping that it will be available next week. thank you, Jon
  9. jpeyron

    pmod wifi

    Hi @harika, I have attached my deWebIOServerSrc.cpp which shows how to alter the # define in the addPINs() function. cheers, Jon deWebIOServerSrc.cpp
  10. jpeyron

    ZYBO license/voucher in Europe

    Hi @Baskoud, We do not sell just the SDSoC voucher by itself anymore. Here is a link to xilinx for purchasing just the SDSoC license. We only have the voucher available for purchase when also purchasing most of are zynq development board as shown here. cheers, Jon
  11. jpeyron

    PMOD CAN with UltraZed

    Hi @Juliano Pimentel, Sorry for any confusion from my earlier post. You have 2 options. First option is to add the AXI_QUAD_SPI IP Core and configure it to communicate with the Pmod CAN. At this point it should not be to difficult to make your own drivers using the Pmod CAN IP Core as a reference. Second option is to open a project with a board selected from an already supported family (zynq, Artix-7), then add the IP to a BD, then edit in IP packager. Then go to the Compatibility Packaging step, "add family, check the "all families and parts" box and then to "review and package", repackage the IP. You should then be able to change the target board and add the IPs you upgraded. Once you have added the upgraded IP core to the block design you will right click on the pmod out of the ip core you are trying to use and select make external. Then after you have created a wrapper you will need to constrain the pmod out pin using the xdc for your board. m and export the hardware including the bitstream. Then launch sdk. Once sdk is open make a new application with the empty template. Then move the main.c file from the examples folder of the Pmod CAN drivers IP core( vivado-library/ip/Pmods/PmodCAN_v1_0/drivers/PmodCAN_v1_0/examples/) to the scr folder of the application. Then program the fpga and run the application. Here is a forum thread that should be helpful with the second option of making the Pmod IP core work with your board. cheers, Jon
  12. jpeyron

    pmod wifi

    Hi @harika, 1) They are the same. 2) Your block design should look like the screen shots that i have attached on the forum thread here. What version of Vivado/SDK are you using? cheers, Jon
  13. jpeyron

    Labview with 7-segment display

    Hi @BROLYNE, Here is an NI tutorial that works with the Nexys 3's 7 segment display that hopefully will be helpful with using the Basys 3's 7 segment display. Here is where you can find the Standard PLD Configuration Files. cheers, Jon
  14. Hi @Abdul Qayyum, On the resource page for the Pmod BT2 here.We have tutorial How to Auto-Connect 2 PmodBT2's Together which describes the process of configuring the Pmod BT2 as a master or slave. thank you, Jon
  15. Hi @jaggu, Unfortunately, We here at digilent do not have MATLAB experience with FPGA's nor do we have MATLAB. Hopefully one of the more experienced community members will have some input for you. I would also suggest reaching out to MATLAB and Xilinx support about your question. thank you, Jon
  16. jpeyron

    cmod-A7 SPI-bootloader starts with second connection

    Hi @Weevil, I have not implemented a software reset in FPGA's before. Here is a forum thread that might be helpful for your situation.Another solution once you have programmed the QSPI you could then program the JTAG. To do this select the program the fpga and changing the microblaze from the srec path back to bootloop. Then program the FPGA. Next right click on the application and run as-> launch on Hardware(System debugger). The normal process to loading the project onto the fpga from SDK. cheers, Jon
  17. jpeyron

    Hello!

    Hi @enrik, Welcome to the forums! You would not be able to use the USB UART bridge using Verilog/VHDL. This is because the USB UART bridge is wired directly to the ZYNQ Processor(PS). If you are trying to use the PS UART not through the USB UART Bridge then you can use the EMIO or MIO pins depending on what you are trying to do. Here is a xilinx forum thread that discusses this. thank you, Jon
  18. jpeyron

    PMOD CAN with UltraZed

    Hi @Juliano Pimentel, We currently do not have the bandwidth to alter the board files and Vivado library IP's to work with FPGA's not currently being used with our products. For the Pmod CAN IP Core i believe we altered the AXI_QUAD_SPI IP Core. You could configure the AXI_QUAD_SPI Ip Core to communicate with the Pmod CAN. At this point it should not be to difficult to make your own drivers using the Pmod CAN IP Core as a reference. Here is a forum thread that should be helpful with the process of making the Pmod IP core work with your board. thank you, Jon
  19. jpeyron

    pmod wifi

    Hi @harika, The demo examples have you add the axi_gpio_ip core to the block design. The example has you connect the on-board switches and led's to the design. The YouTube pmod WIFI tutorial here shows this. I am not able to fully read the errors you are getting in SDK but it looks like either your vivado block design does not include the switches and leds or they are named something else and the XPAR_GPIO_(NAME OF IP BLOCK IN VIVADO)_BASADDR XPARAMETER definition reflect the block design's AXI_GPIO IP cores's name. If you add the Digilent board files and create a project using them the board tab will be available with the pmod ports ,switches and led's. cheers, Jon
  20. jpeyron

    WIN 10 driver issues with digilent cable and Vivado

    Hi @FPGA_matt, Here is a forum thread that addresses an issue with windows 10 and the XUP USB-JTAG Programming Cable that should be helpful. thank you, Jon
  21. jpeyron

    WIN 10 driver issues with digilent cable and Vivado

    Hi @FPGA_matt, Are you using the Xilinx Platform Cable USB II? If so this might be a useful guide. thank you, Jon
  22. jpeyron

    pmod wifi

    Hi @harika, Here is a YouTube tutorial about getting the Pmod WIFI going. It uses the Arty A7 which is not a zynq processor. In vivado you need to be using the Digilent board Files for the Zedboard and the Vivado library. Create a block design and add the ZYNQ processor. Next run block automation under default(board files). The select the board tab. Right click on the Pmod port you wish to use and select the pmod WIFI IP Core. Run connection automation and do not change anything in the Zynq processor. Validate the design, create a wrapper and then generate a bitstream. Everything else should be the same in the YouTube video. You will not need a constraint file do to the board files and Vivado library handling the constraints. thank you, Jon
  23. jpeyron

    PMod for GMS

    Hi @HelplessGuy, We do not have a Pmod GSM. Here is a forum thread where a community member is connecting a GSM module to the Zedboard.
  24. jpeyron

    Using Adept SDK to handle JTAG on ZC706 board: problems.

    Hi @Pavel_47, I have not worked with the ZC706. With that in mind here is the Adept 2 Reference Manual. Here is the Vlab that looks to be using the ZC706 that might be helpful. Here is a forum thread about using the ZC706. Have you looked through the PDF documents in the Adept SDK folder? thank you, Jon
  25. Hi @Kabron, We have reached out to one of our test/design engineers about this thread. They are out of the office for the week. I'm not sure how long it will be before they would be able to respond. I am very sorry about the delay. thank you for your patience, Jon