jpeyron

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Everything posted by jpeyron

  1. Hi @dmishins, Welcome to the Digilent Forums! Please attach a screen shot of your Block design. Did you connect the 200 MHz clock to the MIG as instructed in section 10? What did you set the local memory and cache when running clock automation for Microblaze? best regards, Jon
  2. Hi @Mgilbert, I sent you a PM about this issue. best regards, Jon
  3. Hi @Zhanneta, I have moved your thread to a sub-section where more experienced embedded linux engineers look. best regards, Jon
  4. jpeyron

    Pmod wifi

    Hi @harika, Unfortunately, we do not have the bandwidth to make a YouTube video for the Zedboard and the Pmod WIFI. On your other thread here I have posted a verified working Zedboard/Pmod WIFI project for Vivado 2017.4. that should only need you to alter the HTTPServerConfig.h with your router login and password. best regards, Jon
  5. jpeyron

    pmod wifi

    Hi @harika, Here is a complete and verified Zedboard WIFI project done in Vivado 2017.4. I would suggest to download Vivado 2017.4. You will need to alter the login and password in the HTTPServerConfig.h for it to work with your router. best regards, Jon
  6. jpeyron

    pmod wifi

    Hi @harika, The board connects to the router through the Pmod WIFI. That is why you need the login and password for the router added in the HTTPServerConfig.h. The mode jumper would be set to SD if you were booting your project from the SD card reader. In this case the project is just using the SD card reader and not booting from the SD card reader. You should have the Mode Jumper set to JTAG. best regards, Jon
  7. Hi @TomF, Are you using the Digilent boards files? When doing block automation in vivado I would suggest using 32KB for local and 16 KB for cache. Please attach a screen shot of your block design. What frequency are you giving the ext_spi_clk on the QSPI Flash IP Core? best regards, Jon
  8. Hi @Abdul Qayyum, I would suggest using an enable signal in your UART FSM if you haven't already. For initial implementation i would suggest tying the enable to a button or switch. Also please attach your top/wrapper file as well. best regards, Jon
  9. Hi @Remirod26, We do not have a suggestion for a company that would repair the Arty A7. I sent you a PM about the potential next step. best regards, Jon
  10. Hi @hkhantang, I sent you a PM about this issue. best regards, Jon
  11. jpeyron

    Pmod wifi

    Hi @harika, What WIFI IP Core example are you currently using? If the example is the HTTPserver please attach screen shots of your HTTPServerConfig.h as well as deWebIOServerSrc.cpp. Please attach screen shots of your Vivado block design along with your SDK. best regards, Jon
  12. Hi @tmwhitt, To verify the Pmod AD1 is correctly working please use the Pmod DA1 IP Core with the Pmod Port JA using tutorial link above. Using the Pmod Ad1 IP Core are you getting expected results? Also please attach a picture of you physical set up and Verilog code as well if possible. best regards, Jon
  13. Hi @shahad, I split this thread here so we are not posting on a completed thread. Please attach screen shots of your block design and the top, xdc file. Here is a VHDL Nexys 4 DDR project that uses the USB UART bridge. best regards, Jon
  14. Hi @libswig, Instead of adding the Cora Z7 XDC you should add the XDC file for the ZCU104 found here. I attached a screen shot showing that you will need to expand the associated files to be able to select the xdc for the ZCU104. You should use the Cora Z7 XDC as a reference of what pins will need to be uncommented and how to set up the ZCU104 xdc. I believe you will need to add the clocking wizard from the IP catalog under the flow navigator. Use the settings from the attached screen shots above. best regards, Jon
  15. Hi @Tim S., I reached out to a co-worker that got the same error as you. We dug further into my licenses and it turns out that I have the MIPI licenses and that is why i was not having issues. We also reached out to our content team which suggested to utilize the petalinux releases which include already generated bitstreams and hardware information so you would not need the licenses. As it stands now it sounds like if you are wanting to instead alter the linux base design or use the linux base design for a different linux platform then you would either need to strip out the licensed content or purchase the licenses. In the next few days I will be working on verifying that the petalinux release will not have the licensing issues that are in having in the zybo z7 20 base linux design. best regards, Jon
  16. Hi @mnt, Welcome to the Digilent forums! Are you trying to add a VHDL entity to a zynq processor block design? If that is a yes then right click on an empty portion of the block design and select add a module. Then select the VHDL file. Here is a good YouTube video about this process. best regards, Jon
  17. jpeyron

    xadc_zynq

    Hi @revathi, Here is an article by real digital that provides some additional information about the XADC and averaging. best regards, Jon
  18. Hi @tmwhitt, Welcome to the Digilent forums! To add to @JColvin's post I would suggest looking at a community members ( @hamster ) project here. It is a completed VHDL project that should help with your Verilog project. Are you trying to use both channels? We also have an Pmod AD1 IP Core here found in the Vivado library here . The Getting Started with Digilent Pmod IPs tutorial should be helpful with using the Pmod AD1 IP Core. best regards, Jon
  19. Hi @neroangelo296, Welcome to the Digilent Forums! I moved this thread to a section for FPGA questions. Here is the FMC PCAM Adapter which will allow you to use the PCAM-5C with the Zedboard. Here is the FMC-HDMI that also might fit your needs as well. best regards, Jon
  20. Hi @PoojaN, Welcome to the digilent Forums! 1) Are you programming the QSPI flash through SDK or through Vivado? 2) Here is the Arty Programming Guide and the How To Store Your SDK Project in SPI Flash that should help depending on what type of project you are using. best regards, Jon
  21. Hi @sreehari, Welcome to the Digilent Forums! As of yet I haven't used the LWiP with MDIO commands. Here is a forum thread that discusses MDIO with the Arty ethernet using linux and Here is a non-digilent forum thread that might be helpful. best regards, Jon
  22. Hi @Ram, I have not altered the size of the send buffer for the LWiP. I would suggest reaching out to xilinx about altering the send buffer with their IP. Here is a a xilinx wiki ( wiki ) and here is a forum thread that might be helpful as well. best regards, Jon
  23. Hi @djc678, Welcome to the digilent forum! I have moved this thread to a sub-section where more experienced embedded linux engineers look. best regards, Jon
  24. Hi @osmaan_khan, Here is a forum thread that discusses using the ZYNQ ps with the XADC. There are links to other threads with working zynq xadc projects along with a non-digilent tutorial and the ZYNQ book. best regards, Jon
  25. Hi @Nabil, Welcome to the digilent forums! We have reached out to more experience embedded linux engineers to see if they have some input for this thread. best regards, Jon