jpeyron

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Everything posted by jpeyron

  1. Hi @Allan Flippin, The USB UART connector/programming circuit on the Arty works with microblaze allowing you to debug in SDK. If you were wanting to use the JTAG HS2 as an alternative for configuring/debugging and running an application for the Arty in SDK you can do that to. I just made a simple GPIO/uart project using the JTAG HS2/JTAG connector to program the fpga and run the application which worked with one exemption. Using the JTAG HS2 did not facilitate a com port for serial communication. best regards, Jon
  2. jpeyron

    Vivado free for Artix-7?

    Hi @TerryS, Glad to hear you were able to get Vivado downloaded , installed and get through the "blinky" tutorial! Thank you for sharing what you had to do to get this done. best regards, Jon
  3. Hi @Kris Persyn, I'm glad to hear you were able to get the HDMI project up and running. Thank you for sharing what you had to do! best regards, Jon
  4. Hi @M.Mahdi.T, Welcome to the Digilent Forums! We typically do not test the max throughput metric when validating our products. Looking at the AD5933 datasheet here the Pmod IA would be limited to 1 MSPS due to the on board ADC. The main bottleneck for throughput to a host board will be the I2C communication which runs at 400 KHz. Here is a good forum thread for using the Pmod IA with the Raspberry PI with code and hints for use , setup and calibration. Here is the resource center for the Pmod IA which has the Raspberry PI code as well. best regards, Jon
  5. Hi @PG_R, I have connected many different fpga's to my PC through Ethernet using a standard Ethernet cable. I believe a regular ethernet cable will do just fine. The difficult process will be facilitating the ethernet communication. That is why I suggested using the petalinux project linked above. best regards, Jon
  6. Hi @Allan Flippin, Here is the VHDL code for the UART TX from our GPIO demo for the Arty-A7-100T which sets the tx baud rate to 9600. I have not used auto baud detection since typically we dictate the baud rate in our projects. best regards, Jon
  7. Hi @Allan Flippin, If you use the Arty-A7 35T or 100T or the Arty-S7 50T or 25T you can use a HDL(Verilog/VHDL) UART controller to communicate through the USB UART bridge. ZYNQ FPGA's have some of the components on the board tied directly to the Arm processor(PS). The DDR3 and USB UART bridge would be included in these components. With ZYNQ FPGA's you can not use the PL to directly use the USB UART bridge. I have attach an image that is a good reference on the ZYNQ processor. To use the USB UART bridge with the Arty-Z7 20 or Arty-Z7 10 you would need to use the Zynq processor. Here is the getting started with ZYNQ tutorial for the Zybo that can easily be used with the Arty-Z7 . The GSWZ tutorial shows how to use the PS to communicate through the USB UART bridge. Here is the Arty-Z7 , Arty-A7 and Arty-S7 resource centers. best regards, Jon
  8. Hi @hmd, I'm glad to hear that the command which vivado helped you find the path needed to complete the installation. Thank you for sharing what you did. best regards, Jon
  9. Hi @kwilber, Thank you for sharing. This book looks awesome! cheers, Jon
  10. Hi @vttay03, I have not been able to be able to get the Hello world template to work with the QSPI flash with either the Arty-A7 35T or the Arty-A7-100T in Vivado 2018.3. I will keep looking into this issue with Vivado 2018.3. For now I would suggest using Vivado 2017.4. I was able to complete and verify the Hello world template project into the QSPI flash on the Arty-A7-100 using Vivado 2017.4. I attached some screen shots of the programming setting in SDK. Also the offset is 0x003D0900 since the HW platform size is the same as the Nexys 4 DDR which has the same FPGA. best regards, Jon
  11. Hi @hmd, I opened my VM and looked opt/ from the root directory. It has the Xilinx/ directory. I think it would be best to uninstall and re-install Vivado an leave it to default settings. Make sure that you are root while installing Vivado to insure there is no issues with permissions. best regards, Jon
  12. Hi @PG_R, I do not have much experience connecting two FPGA's together through ethernet. Initially I do not see any reason that you would not be able to connecting these boards together through ethernet. I would suggest using the Petalinux project for the Zybo Z7 to facilitate the ethernet. best regards, Jon
  13. jpeyron

    Genesys 2 DDR Constraints

    Hi @SeanS, @JColvin response was also my thoughts based on the screen shot. The color scheme of the MIG page attached looks like ISE. I am glad that you are now able to get the MIG default setting to be pre-set by the board files. best regards, Jon
  14. Hi @hmd, Change directory(CD) to the root directory and run the command s -l there. Its been a little bit since I have played around with Linux in my Virtual machine. I believe the OPT directory is there. Sorry about the mis-information. best regards, Jon
  15. Hi @FPGAMaster, The programming circuit is considered proprietary. I have PM'd you the next step in regards to the programming circuit. best regards, Jon
  16. Hi @Allan Flippin, It's my understanding that there is no current plans on adding access to the memory like for the newer families of FPGA's in Adept 2. I am also not aware of any other application that facilitates that type of interaction with memory. If using the USB UART bridge is a feasible alternative, could you be more specific about your data rate needs for transferring/receiving data to the PC? There are quite a few HDL(VHDL/Verilog) UART Controllers available with a quick google search. We also have projects that transfer data through the USB UART bridge using HDL like the Arty-A7 100T GPIO demo. This older tutorial uses the Microblaze processor and uart lite IP Core that uses the USB UART bridge as well. best regards, Jon
  17. Hi @Allan Flippin, The memory functionality you discuss above for the Nexys 3 is not facilitated for the newer FPGA families like the Artix-7 and ZYNQ. Adept 2 does still allow users to configure newer xilinx FPGA's using .bit files. Adept 2 can be downloaded here along with the Adept 2 reference manual. best regards, Jon
  18. Hi @hmd, 1) Did you install Vivado 2018.3 on a different drive? 2) Was vivado 2018.3 installed at the default path? 3) Please attach a screen shot of the command " ls -l " when in the home/ and the opt/ directory. Also make sure that you are root. best regards, Jon
  19. Hi @ToronoCoyo, Welcome to the Digilent Forums! Typically for more complicated projects such as the PCAM project doing connection automation with the same IP Cores alone will not create a HW platform that will correctly interact with the desired components. Can you include screen shots of your block design and SDK applications and any errors along with wrapper, xdc and SDK helloworld.c files. What is the Mode Jumper(JP5) on the Zybo-Z7 set to? If you are trying to boot from the SD card on a ZYNQ development board like the Zybo Z7 you should be making a boot.bin file. Booting from either SD card or FLASH process is described in this older zedboard tutorial. best regards, Jon
  20. Hi @Allan Flippin, Adept 2 and Adept 2 SDK does work with Artix-7 based FPGA boards. Some of the functionality that was available for older FPGA's in Adept's UI was not done for the newer FPGA. The Vivado Hardware manager can write to FLASH and can read ILA files. The ILA IP Core which is Vivado's version of chipscope is available at no cost with the free Vivado Webpack edition. Here is a good reference to what is available for each Vivado edition. You can also use the USB UART bridge or ethernet to transmit/receive data from a PC using Microblaze or HDL for non-zynq families and the Zynq Processor with Zynq FPGA's. I have used the USB UART bridge and serial terminal emulator(tera term) to send/receive data for trouble shooting issues in Artix-7 project development. best regards, Jon
  21. Hi @jaypdx, I have passed on your suggestion to our content team about warnings for back powering through the HDMI. I will mention your suggestion about adding protection for this to our design team. best regards, Jon
  22. Hi @jaypdx, You should either turn off the HDMI monitors that are connected to the Arty-z7 or unplug the HDMI cables prior to turning off the Arty-Z7. You can back power the Arty-Z7 through the HDMI connectors. This can cause potential issues with the Arty-Z7 startup power sequence which could affect your project. Its my understanding that back powering could potentially cause damage as well. best regards, Jon
  23. Hi @jaypdx, Welcome to the Digilent Forums! Vivado projects are version specific and are not always easily upgraded to a different Version of Vivado. In this case, both the HDMI-OUT for the Arty-Z7-20 and the Arty-Z7-10 were last updated to "Vivado 2018.2". It does sound like you have upgraded it correctly since you are able to get it to work. I would suggest to press PS-RST button which is connected to a dedicated pin on the FPGA. The PS-RST button will reset the Processing system of the Zynq. I believe you should be able to re-run the application without an issue after you press the PS-RST. best regards, Jon
  24. Hi @Ajeeth_kumar, Glad to hear you were able to get your project working. Thank you for sharing what you did. cheers, Jon
  25. Hi @Anusha Kodimela, You can design a converter in your hdl which takes in binary 8 bit value from the FIFO and converts it to ascii hex before transmitting to the PC using the USB UART bridge. The other option is once you have transmitted the data to the pc you can use a program to convert the 8 bit data to ascii hex and then read it on the terminal. best regards, Jon