jpeyron

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Everything posted by jpeyron

  1. Unable to add modules to designs

    Hi @Android, I have not worked with interrupts in microblaze very much. I did not see anything wrong with the SDK code specifically. Here is a forum thread about interrupts. Here is a link that discusses using microblaze and interrupts. Can you attach your project? thank you, Jon
  2. Ready to use Linux Image for Zybo Zynq 7000

    Hi @dentiloque_roc, Here is the Petalinux Support for Digilent Boards that has a newer link for the Zybo bsp . thank you, Jon
  3. XVC problem in Vivado 2017.4 with Zybo Z7-20

    Hi @rhb, Glad to here that it looks like the debian installation was successful. I have passed on your suggestions to our content team. thank you, Jon
  4. Vivado slowness reality check

    Hi @gwideman, It depends on the number of cpu's you choose as well as the ram size/type your pc has. It also greatly depends on the board and project size you are generating a bitstream for. I have had this process take anywhere from 10 - 45 minutes. I have and I7, with 16 GB of ram on windows 7. cheers, Jon
  5. HOW TO PERMANENTLY PROGAM NEXY4 DDR

    Hi @flexible111, I had a hard time getting your project to load correctly on my PC. I made two different projects in Vivado 2017.3 one with a non-compressed bitstream and one with a compressed bitstream and verbose is commented out in the srec bootloader so the project loads super fast. You will need to install the board files following the Vivado Version 2015.1 and Later Board File Installation tutorial. When you open either project first go into the project setting and set the IP repo to your vivado library path. Then you can open the block design and see what the block design looks like. You do not need to generate the bitsream again you can just launch SDK using the existing bitstream. Once SDK opens you will program the fpga and then load the .elf file with the offset as 0x003D0900 for either project and download.bit file (0x0) with the mode jumper on qspi. Then you should only need to turn off the Nexys 4 DDR and turn it back on. I used the same Pmod port JC as was in your project. Here is the non-compressed project and here is the compressed project. The compressed project will not send information out through the uart since I commented out verbose in the bootloader.c in the srec application. thank you, Jon
  6. Hi @pollutioncontroltech, I do not have experience with high speed cameras like that. I did find a link here that might be useful. thank you, Jon
  7. Hi @pollutioncontroltech, I do not believe you will be able to get the FPS you are looking for. The product brief shows the max image transfer rate. The highest fps i can see is 120 fps at 320 x 240. It also shows this in the datasheet for the OV05640-A71A. QSXGA (2592x1944): 15 fps 1080p: 30 fps 1280x960: 45 fps 720p: 60 fps VGA (640x480): 90 fps QVGA (320x240): 120 fps thank you, Jon
  8. BLOCK Design VIVADO UD CNTR Q[?:?] to Discrete logic [?:?]

    Hi @DigitalConfig, The xdc would be here for the Arty-A7-35T then. Also Arthur reminded me about a better option then "make external". Select "Create Interface Port" instead. You have a lot more options for what you want and you can dictate what pin name the wrapper will use. cheers, Jon
  9. Zybo Z7 Pcam 5C Demo - AP transaction error

    Hi @Vijay_sr05, Is the mode jumper JP5 on the Zybo-Z7-20 set to JTAG? Did you change anything in the zynq processor in the block design in the Vivado 2016.4 project? Are there any errors when you generated a bitstream in vivado? Any errors in the sdk under problem tab? If so can you attach screen shots? Are you able to make a project using the preset board files for the Zybo-Z7-20 in vivado 2016.4? thank you, Jon
  10. BLOCK Design VIVADO UD CNTR Q[?:?] to Discrete logic [?:?]

    Hi @DigitalConfig Based on your other threads are you using the Arty-S7-50? Here is the master xdc for the Arty-S7-50. On the blocks that you want the output to go to pins on the board you right click on the out bus and select make external. Once done with your design you select the source tab and right click on the design block and select create a wrapper and click ok. Then you use the xdc to constrain the pins names generated in the wrapper with the xdc. thank you, Jon
  11. Zybo hdmi in demo project resolution issues.

    Hi @Shuvo Sarkar, Have you tried re-reacquiring the VGA image from the monitor after changing the resolution to 720p? Could you attach picture/screen shot of what you are seeing?
  12. VGA Pmod Tutorials

    Hi @Flux, Thank you for making and sharing these tutorials for the Pmod VGA! I have moved this thread to the Project vault. thank you, Jon
  13. Looking for Statement of Volatility for Arty models

    Hi @jeffjackson, Here is the Statement of Volatility Arty A7-35T , Statement of Volatility Arty_Z7_10 and the Statement of Volatility Arty_Z7_20. thank you, Jon
  14. Verification setting via usb-otg question

    Hi @Elect_GD, You will need to use an embedded linux platform to use the OTG USB on the Zedboard. I believe that you can also accomplish your desired verification using an embedded linux platform. The Zedboard comes with a sd card having a basic embedded linux platform on it. Here and here are some tutorials and projects with petalinux for the zedboard. Here is a wiki/tutorial for petalinux as well. thank you, Jon
  15. Zybo Z7 Pcam 5C Demo - AP transaction error

    Hi @Vijay_sr05, To clarify, you are first programming the FPGA and then running the application(run as->launch on hardware(system debugger))? thank you, Jon
  16. Hi @oceley, We do not have the max temperature metric. I do know that the XC7A200T-1SBG484C on the Nexys Video is commercially rated 0 to 85 degrees Celsius. thank you, Jon
  17. DjtgEnable and DjtgDisable take a long time to complete

    Hi @Jim H, I talked to our design engineer and they responded with "a server/client setup the server opens and enables the port and performs all calls to the DJTG API. The clients make no calls to the DMGR or DJTG API. The end result is a single process that directly accesses the device. All client processes must communicate with the server process to transfer data. The only devices that Digilent makes that support 2-wire JTAG are the HS2 and SMT2. They both use the same drivers and USB controller, and thus will have equally slow enable and disable operations. I’m unware of any good way to speed up enable/disable operations, which means the only solution is to implement a client/server application as I described above, or find another cable that supports 2-wire mode and hope that it doesn’t have similar issues." thank you, Jon
  18. Zybo Z7 Pcam 5C Demo - AP transaction error

    Hi @Vijay_sr05, I would exit SDK and delete the pcam-5c.sdk file in the proj folder. Then I would go to the vivado project again and re-export the hardware including the bitstream and launch the sdk from vivado. Then re-import the applications and see if this solves the issue. You are also programming the fpga before running the application as shown in the screen shot below. thank you, Jon
  19. Zybo-Z7: SDK seems broken, cannot finish the guide

    Hi @freakuency, With the DMA project are you using tera term for the serial terminal? I believe the buttons control the state of the project. So you are using the buttons and not recording or playing back? Are you able to run any of the other linked projects on the resource center? thank you, Jon
  20. PmodMIC3 Frequency Response

    Hi @bikerglen, We are looking into your question. Sorry for the delay in a response. cheers, Jon
  21. HOW TO PERMANENTLY PROGAM NEXY4 DDR

    Hi @flexible111, I apologize, I was out of the office the last couple of days and did not have access to a Nexys 4DDR. I will get to this as soon as I can. I am sorry for the inconvenience. It may be a couple of days due to activity on the forums. thank you, Jon
  22. Hi @Thausikan, I havent worked with LVDS so would not have any input for you. I have reached out to my co-workers to see if they have any recommendations for you. thank you, Jon
  23. Zybo Z7 Pcam 5C Demo - AP transaction error

    Hi @Vijay_sr05, I was able to generate a bitstream without and issue in Vivado 2016.4. I then export the hardware incluting the bitstream and launch sdk from Vivado. Once SDK is loaded I import the applications from the SDK folder. I then program the fpga. Next I right click on pcam_vdma_hdmi and run as->launch on Hardware(system debugger). It loaded onto my Zybo-Z7-20 without an issue. I have included some screen shots. The applications are greyed out from my import screen shot since I had already imported the applications to my project. cheers, Jon
  24. CMOD A7 - LVCMOS1.8V?

    Hi @jon darl, Here is a xilinx forum thread discussing using LVDS 1.8v as an input on a pin that connected to a 3.3v bank. It appears that you would be able to get input at 1.8 but not tx in the lower voltage. We do not recommend altering our boards. If you were to alter the board and gain access to the 1.8 rail through the I/O pins this would undoubtedly break other components on the board. thank you, Jon
  25. Zybo-Z7: SDK seems broken, cannot finish the guide

    Hi @freakuency, Another option would be to download Vivado 2016.4. The version does matter when dealing with demos. This project was made in Vivado 2016.4 for Vivado 2016.4. thank you, Jon