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Everything posted by jpeyron

  1. Microblaze Xintc_SelfTest Failure w/ Baseline ARTY BSD

    Hi @macgyverque, I was able to get the testperiph.c to run without an issue using the Arty-BSD project as shown below. Make sure to press buttons when asked in the terminal text. I was also able to run the xintc_example.c here with a small change to the BSD project in Vivado. I had to add one more input on the xlconcat going from In0-In6 to In0-In7 inputs. Then I connected In7 to the interrupt on the UARTLITE IP Core. I successfully ran the xintc_tapp_example.c here as well. Could you take a screen shot of your block design and attached the SDK code. cheers, Jon
  2. Zybo demo projects in Vivado 2017.1

    Hi @chrislafave, Glad to hear you were able to get the IP's to upgrade. cheers, Jon
  3. Hi @Jagbandhu Sahu, I do know that the JTAG-HS2 works with the ARC processors. Unfortunately we do not have any information about the ARC processor. You will need to contact Synopsys for assistance in developing an application which can read and write RAM memory of the controller using Digilent HS2 JTAG cable. thank you, Jon
  4. PikeOS project on ZC702

    Hi @Atir, Unfortunately, I am not aware of anyone at Digilent that is familiar with PikeOS. We support Petalinux. Hopefully one of the more experienced embedded linux community members might have some information about this. I would also suggest reaching out to SYSGO here since they are the creator of PikeOS. thank you, Jon
  5. Micro SD Card Slot on ZYBO Board

    Hi @talentlyb, I have sent you a PM about the next step for this situation. cheers, Jon
  6. JTAG-SMT2 usb tabs

    Hi @tbonnefond, I had talked about this with our senior layout and design engineers previously about a similar thread here and their response was that the electrical keep out areas are flush with the PCB and will not cause issues with it seating on the target PCB. You should not need usb slots. cheers, Jon
  7. Zybo demo projects in Vivado 2017.1

    Hi @chrislafave, Are using our original Zybo HDMI-OUT project here made in Vivado 2015.4? The tcl script is here: hdmi_out/src/bd/system.tcl? I just completed bitstream on the zybo hdmi-out project in Vivado 2017.1. I would suggest to used a project that you have not made changes to or opened with vivado yet. Make sure you are using the Vivado 2016.4 version of the Zybo HDMO-OUT here. Make sure that you have downloaded and added the contents of the vivado library from here in the repo\vivado-library folder here: Zybo-hdmi-out-master\repo\vivado-library. Then edit the hdmi_out_bd.tcl from 2016.4 to 2017.1 here: Zybo-hdmi-out-master\src\bd\hdmi_out\hw_handoff. After editing load the project in Vivado 2017.1 , upgrade the IP cores by going to tools->reports-> report ip status. Next create a wrapper and then generate a bitstream. cheers, Jon
  8. Hi @gm_, I was mistaken with question 1, to clarify: The JTAG-HS2 works in Vivado and iMPACT under Fedora. Sorry for the confusion, Jon
  9. No Compatible Board Interface

    Hi @FarmerJo, Certain parts of the Zybo are tied directly to the Zynq processor such as the UART. I have attached a screen shot of the zynq processor. This makes the task of learning Microblaze much more difficult on the Zybo. You will need to research how to use the Zynq and Microblaze processors together. Unfortunately, I have no experience with this. edit: Here is a Xilinx forum thread that deals with this issue on a Zedboard with has a ZYNQ processor as well. thank you, Jon
  10. Zybo demo projects in Vivado 2017.1

    Hi @chrislafave, Here is a forum that has the process to get the Zybo projects working in the new versions of Vivado. In the thread I am doing it for Vivado 2017.2 but you just need to use 2017.1 instead. So far I have not had any issues with this process. Let me know I you are not able to get the project working. cheers, Jon
  11. Arty XADC external voltage input

    Hi @Nystflame, I follow the getting started with microblaze tutorial here with a couple of changes. After step 3.7 I edit the MIG and on step 5 I also add the xadc wizard, configure it , make the vaux 0,4,5,6,7,15,vp/vn external pins and connect the device out on the mig to the xadc for temp. I next make a wrapper and add the xdc file I have provided. I am able to get the VP/VN correctly working and I am getting voltage reading out of A0-A5. You only put the positive in A0-A5 with the negative already ran to ground I included a screen shot of the schematic show this. The VP/VN is the only one that I made that needs a p and n connected. I have attached a screen shot of my block design, the xadc wizard settings and disabling the xadc in the MIG. I have also included my xdc and my sdk code. In sdk use the hello world application and copy paste the code i have provided into the hello world. My vn/vp reading are right one but A0-A5 voltage reading are not correct. I am still working on the A0-A5 issue but might not be done right away. cheer, Jon arty_xadc_xdc.txt arty_xadc_sdk.txt
  12. Unable to Install Waveforms 2015 on Linux

    Hi @jlauer, I have moved your forum thread to section where more experienced Adept 2 and WaveForm 2015 forum members look. I had a similar issue when installing Waveforms 2105 on my Ubuntu 16.04 VM. I had to install the Adept 2 runtime file first and then Utilities and WaveForms 2015 would install. cheers, Jon
  13. Hi @skaat27, I have reached out to a more experienced embedded linux co-worker about your forum question. They are out of the office this week and probably will not be able to respond until later next week. I am sorry for the inconvenience. thank you, Jon
  14. 210-251 height

    Hi @tbonnefond, On the bottom of the resource page for the JTAG-SMT2 has a 3D CAD model that should have that information for you. cheers, Jon
  15. Unstable data received from HDMI/DVI to RGB converter

    Hi @tuan, Unfortunately I do not have enough experience to be helpful with you project. I have reached out to my co-workers to see if they have any input. thank you, Jon
  16. Hi @metso, I looked at the BOM for the MAX32 REV C and REV D and X1 is FQ7050B-8.000. cheers, Jon
  17. Hi @Dean@L3, Glad to hear you are able to get the spi flash working. Thank you for sharing what you did and what you have found. cheers, Jon
  18. Micro SD Card Slot on ZYBO Board

    Hi @talentlyb, Unfortunately we do not repair broken products. We do have an RMA process depending on circumstances and time you have had the product. How long have you had the Zybo? When you push the sd card in the slot does the Zybo still recognize the sd card? Was there a situation that caused the sd card reader to stop working properly I.E. something falling on the board. thank you, Jon
  19. No serial port when connecting to shared JTAG/UART USB

    Hi @clara.daia, Here is a forum thread that deals with using a serial terminal in linux. When I first made was using my ubuntu 16.04 VM I had issues communicating to a serial terminal. So first i made sure i was part of the dailout group sudo adduser $USER dialout then I sudo apt-get install screen then I'n my case I needed to use ttyUSB1 look in dev to see if ttyusb0 or ttyusb1 is available? To start the serial terminal the command i used was: screen /dev/ttyUSB1 115200 cheers, Jon
  20. Channels in the XADC

    Hi @cristian_zanetti, Tomorrow i will run our nexys 4DDR xadc project and try to get multiple channels going at the same time. I would also suggest looking through the 7-series xadc user guide. cheers, Jon
  21. how to flash multiple elf files on zybo

    Hi @Axe, Unfortunately I do not have any experience with using two elfs at the same time in bare metal or with the first stage bootloader. I have reached out to my co-workers and see if they have any input for you. I would also suggest reaching out to Xilinx support about this as well here.
  22. VFBC max clock frequency for Atlys

    HI @chcollin, I have not been able to find any additional information that would help to find the maximum frequency that can be used for the VFBC interface clocks for the Spartan 6. My co-worker that responded to your Atlys HDMI demo questions is out of the office for a week so would not be able to give any input to this thread until later next week. I would also suggest reaching out to Xilinx about this as well here. cheers, Jon
  23. Arty temperature grade

    Hi @Federico, On the resource page here we show the FPGA on the Arty Artix-7 as the xc7a35ticsg324-1L. If you look at the Artix-7 FPGAs Data Sheet: DC and AC Switching Characteristics here. It breaks down to device type, package, speed and temperature grade. Device : XC7A35T package: CSG324 speed grade : -1L temperature grade: i for industrial which is -40 to 100 degrees C cheers, Jon
  24. @Dean@L3, I would make a fresh project using the 50 Mhz clock from the clocking wizard connected to the ext_spi_clk on the quad spi ip. You are able to run the hello_world application an set it in the terminal correct? Tomorrow is will add my project to google drive and see if you can run it. cheers, Jon
  25. Hi @Dean@L3, I believe that the erase is only for the region of the flash that you are putting in new data as described here and not the whole flash. The path name looks correct. Are you using tera term as the serial terminal? I suggest using the getting started with microblaze tutorial for building the block design in vivado. The only two differences is when you are configuring the output clocks in the clocking wizard I also add a 50 MHz clock and when adding the uart I also as the axi quad spi. I then add the 50 MHz output clock from the clocking wizard to the ext_spi_clk on the axi quad spi IP core. Can you attach a screen shot of you block design from Vivado? cheers, Jon