jpeyron

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jpeyron last won the day on August 22

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About jpeyron

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  1. Hi @CaptFraz, Unfortunately we do not have a dimensional engineering drawings for the Cora Z7. best regards, Jon
  2. Hi @SeanS, Looking at the Genesys 2 schematic there is not a 100 ohm line to line controlled impedance routing for differential pairs that go to the HA, HB, and LA banks on the FMC connector. best regards, Jon
  3. Hi @chaitusvk, Are you adding the link to the IP core in " settings->ip->ip repository "? Please attach screen shots of your situation so that we can better assist you. Here is a tutorial that might be helpful as well. best regards, Jon
  4. Hi @mohammad poorkhalili, Welcome to the Digilent Forum! I sent you an PM about this. best regards, Jon
  5. Hi @CaptFraz, We still do not have 3D CAD files available for the Cora Z7. I have passed on your request to our content team. best regards, Jon
  6. jpeyron

    Webserver using Zybo Z7

    Hi @sgandhi, I have attached a SDK file that uses the SD and GPS that should be helpful. best regards, Jon main_gps_sd.c
  7. jpeyron

    Firmware via Android

    Hi @Taras, To clarify, you are looking to use and iMPACT like app on an android tablet to program a spartan 6? I'm not aware of an Android App that configures Xilinx FPGA's. The Digilent Adept 2 here can configure FPGA's but is not compatible with the Android OS. Adept 2 can configure some flash devices but is limited. What specific spartan 6 are you using? If it is one of Digilent's spartan 6's like the Nexys 3 you could use the USB host with an USB thumb drive. A USB thumb drive with a bit file can configure the FPGA on start up. In the section 1 Configuration and the 7 USB HID Host of the Nexys 3 reference manual discusses this. best regards, Jon
  8. jpeyron

    FPGA

    Hi @CKV, Glad to hear that the issue has been resolved. best regards, Jon
  9. jpeyron

    hI!

    Hi @bixie, Welcome to the Digilent Forums! best regards, Jon
  10. Hi @miner_tom, Looking at your screen shots, it looks like the board is showing as COM8 in the ports section and both converter a an b are showing in the Universal serial bus controller section. Please download Adept 2 here. Does the Adept 2 recognize the Zybo-Z7-20? I attached an example of this using a Cora Z7. Does Vivado's Hardware Manager recognize the Zybo-Z7-20? Is the mode jumper set to JTAG? best regards, Jon
  11. Hi @JT2, Under the release tab for the Nexys A7 100T here: https://github.com/Digilent/Nexys-A7-100T-OOB/releases select the Nexys-A7-100T-OOB-2018.2-1.zip and it will download the appropriate folder and files within. I have attached screen shot showing the process and the contents of the zipped folder. best regards, Jon
  12. Hi @Abhijit, Please attach your wrapper and xdc files for your current projects. Here is some non-digilent HDL tutorials here and here that show how to use the Pmod VGA with the Arty-A7. The tutorials cover displaying an image. best regards, Jon
  13. Hi @shyams, When I looked further into the helloworld.c it appears that the interrupt functionality is not being used. I created a Arty-A7-35T Vivado 2018.2 gpio interrupt project here using the xgpio_intr_tapp_example.c provided by xilinx SDK code found here: C:\Xilinx\SDK\2018.2\data\embeddedsw\XilinxProcessorIPLib\drivers\gpio_v4_3\examples. Looking at the main function of the xgpio_intr_tapp_example.c the main function does not poll for data but rather uses the GpioIntrExample function. I have attached screen shots of the Vivado block designs. best regards, Jon
  14. Hi @miner_tom, Are you using the Zybo Z7-20 or the Pynq Z1 as described in your previous post here. When you are creating a project are you selecting the correct board under the boards tab. I have attached a few screen shots for a project using the original Zybo. In windows are you able to see the Zybo board in the device manager under the ports and universal serial bus controllers section? best regards, Jon
  15. Hi @zitong Xu, Welcome to the Digilent Forums! I think this post is beyond the scope of this forum. I would suggest reaching out to Xilinx support about this. Maybe one of the more experienced community members will have some input for you. I did find a xilinx thread here and here that might be helpful. best regards, Jon