jpeyron

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Everything posted by jpeyron

  1. Hi @pls_seniordesign18, Welcome to the Digilent Forums! 1) Here is the resource center for the Nexys A7. I would suggest going through all of the tutorials. 2) We have an IP core for the Pmod SF3 in the Vivado library here. 3) The Pmod SF3 resource center has a link to the IC's Data Sheet. The data sheet describes how to configure and communicate with the IC. I would suggest first getting the Pmod SF3 IP Core working with the Nexys A7 . Then use a bread board to break out the lines between the Nexys A7 and the Pmod SF3 using the Analog Discovery 2's logic analyzer to see how to configure/communicate with the Pmod SF3. 4) Once you have a good understanding on how to configure/communicate with the Pmod SF3 you should be able to use the Analog Discovery to interact with the Pmod SF3. thank you, Jon
  2. Hi @MassiCutug, Typically, the QSPI mode is intended to configure the QSPI Flash with a BOOT.BIN in SDK(ZYNQ processor) and not configuring the FPGA directly. I do believe the QSPI mode still allows the FPGA to be configured from the QSPI mode. It is an odd behavior that the QSPI Flash OOB demo is configuring the ZYNQ processor but the OOB demo is not quite the same as before. As well as the ZYBO Z7 in not showing up in Vivado with the mode jumper set to QSPI. 1) I would suggest trying to re-configure the OOB demo and see if the board is still exhibiting the same behavior. For the ZYBO Z7 OOB demo on the QSPI flash we actually don't load the SPI flash using an MCS file, we copy the needed files using Linux manually. Use the linked package to load the QSPI back to default state. Place these files on a micro SD card and boot the ZYBO with it. After ~4 minutes, the QSPI will have been programmed with the default image (there will be some terminal output indicating what is going on). https://www.dropbox.com/s/ark7wz4md7s6zod/sdlinux_Zybo.zip?dl=0 2) Also here is an older Zedboard programming tutorial that is usable for the ZYBO-Z7 that describes how to make and configure a ZYNQ processor with a BOOT.BIN file . If you are wanting to add a different project to the QSPI Flash you can. thank you, Jon
  3. jpeyron

    Zybo HDMI output help

    Hi @Kris Persyn, Its my understanding that the hardware on the Zybo boards are not able to support 4k resolution. thank you, Jon
  4. Hi @JLDIJDYI, The ESD protection Diodes D1 ,D3, D5 ,D7, D9 are NSQA6V8 SOT-323-5 ON Semiconductor Quad Diode Array for ESD protection. cheers, Jon
  5. Hi @Mukul, Here is a completed and verified Zybo-Z7-10 Getting started with Zynq project done in Vivado 2018.2. 1) Please download and run this project. Does this project work for you? When you started you project did you select the zybo z7-10 board file as shown below. thank you, Jon
  6. jpeyron

    pmod wifi

    Hi @Gourav, Here is a forum thread that discusses taking data from the DVI2RGB IP and connecting it to the AXI bus to store the data in the DDR that might be helpful. If you can get the DVI2RGB data to be stored on the DDR then this point you should be able to access the DDR memory and send it through the server/client WIFI setup. thank you, Jon
  7. Hi @Ahmed Alfadhel, Glad to hear that the UART is now working and you have the microblaze input at 333 MHz. thank you, Jon
  8. Hi @tfcb, Here is the PmodISNS20 resource center. I altered the INO from the MPIDE example without a shield to use the SPI library instead of the DSPI library and have attached it below. It compiles without issue but is untested. You will need to alter the CS_PIN to reflect the cs pin on your microcontroller. thank you, Jon Pmod_ISNS20_example.zip
  9. Hi @Ahmed Alfadhel, I re-opened the project i linked and you are correct the clk off of the microblaze is at 83 mhz. Sorry for the mistake. It is not 100 MHz but rather 83 MHZ. The clock connection is the same setting in the FPGAdevelopers's video as well. This is the suggested setting for configuring the Arty-A7-35T. Its my understanding that we chose the 166.667 MHz clock in the clocking wizard do to an issue with the DDR. To try and possibly gain additional performance by increasing this clock you will need to research configuring the microblaze . You will also need to research all of the other components using this clock and configure them appropriately. thank you, Jon
  10. Hi @Christine Nason, I have sent you a PM about this. cheers, Jon
  11. Hi @Mukul, I would suggest to start fresh and delete the .sdk folder. 1) Then re-export the hardware including the bitstream and launch sdk. 2) Then create an application and add the SDK code in the tutorial. thank you, Jon
  12. Hi @Ahmed Alfadhel, I followed the FPGAdeveloper video as best as i could using Digilent's board files. When selecting Application in block automation of the microblaze it grays out one of the cache choices. The microblaze clk shows 100 MHz after finishing block automation. I generated a Vivado 2018.2 Arty A7 35T microblaze uart project here using the Arty - Getting Started with Microblaze as reference. The clk is 100 MHz. I have attached screen shots showing this below. thank you, Jon
  13. Hi @Hunaina, Here is a xilinx forum thread that discusses the Error Labtools 27 3165 End of startup status LOW. They state that "There are two reasons that the voltage could drop, first that it exceeds the capacity of the supply, and second that the sudden increase in current causes the supply to dip briefly and there is not enough bulk bypass capacitance to hold the voltage above the minimum required to retain configuration." 1) What is the spec's for your wal- wart you are using to power the Zedboard? thank you, Jon
  14. Hi @Mukul, 1) Please attach a screen shot of your Vivado block design. 2) Are you using the Digilent board files? 3) why is there a verilog_HW_platform in your Project explore tab of the SDK? cheers, Jon
  15. Hi @regnon, 1) Yes the Arty-Z7 and the Zybo-Z7 use the same Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port. 2) The digilent board files should be configuring the ethernet correctly. You should not need to alter the default settings(given you are using the Digilent board files). 3) Are you changing anything in the ZYNQ processor or doing anything different from the getting started with ZYNQ server? 4) Another suggestion would be to try a different Vivado version like Vivado 2017.4 or Vivado 2016.4. The xxxx.4 version of vivado is typically the most stable and bug free. thank you, Jon
  16. Hi @atluft, J9 is labeled on the bottom of the Arty-S7 as shown on the screen shot below. J9 is shown on the top of page 6 of the schematic for rev E here. J11 is on the bottom of page 10 of the schematic. Please attach a picture of J11 and J9 if your Arty-S7 rev E is not labeled as shown below. cheers, Jon
  17. Hi @carcher, I moved your thread to a section when more experienced embedded linux engineers look. thank you, Jon
  18. Hi @Ahmed Alfadhel, To confirm you were getting uart communication. Then you alter the frequency to 333 MHZ the uart stopped. I would think that changing the frequency could be the issue. I would suggest altering back to the original frequency and then testing the uart. The digilent board files are made to correctly configure the ddr and microblaze among other thing. Why are you changing the frequency? thank you, Jon
  19. Hi @Jubullu22, I had some issues trying to upgrade this project directly to 2018.3. To get past the vivado issues i had to generate a bitstream using Vivado 2018.2 and then open the project using VIvado 2018.3. Here is the unverified project vivado 2018.3 Nexys A7-DMA-audio demo. thank you, Jon
  20. jpeyron

    pmod wifi

    Hi @harika, I have not ran into the error lock down A303 error before. I did find a refernce to a error lock down A304 on this Xilinx forum thread. 1) I would suggest not having the Linux files on the SD card. 2) Here is the zedboard reference manual. What mode setting do you have on the Zedboard (page 28 and attached screen shot). 3) In regards to the Zynq processor make sure you are using the digilent board files. The board files become the default setting for the ZYNQ processor when you are running block automation. I would suggest not altering the default settings, until you have a working project. Then I would worry about optimizing the project. thank you, Jon
  21. Hi @SethK, Welcome to the Digilent Forums! cheers, Jon
  22. Hi @neocsc, Here is a verified Nexys Video HDMI project updated from Vivado 2016.4 to Vivado 2017.4. You should be able to find the updated project in the proj folder . Here is a GitHub project done in HDL using the clocking wizard, DVI2RGB and RGB2DVI IP Cores for another FPGA. Here is a unverified Nexys Video Vivado 2017.4 HDMI pass through project made from the linked Github project. In the next few days I should have the bandwidth to verify this project. thank you, Jon
  23. jpeyron

    Nexys 3 Pmod Nav Problem

    Hi @NiLo, I have not found any verilog projects with the PmodNAV. I did find a FPGA-Based Real-Time SLAM paper that might be helpful. cheers, Jon
  24. jpeyron

    Nexys 3 Pmod Nav Problem

    Hi @NiLo, Here is the Vivado Library which has IP cores for most of our Pmods including the PmodNAV. I would look at our driver to see how we solved this. I would look at the following functions in the PmodNAV.c. I would also look at the following functions in main.c thank you, Jon
  25. Hi @Hunaina, Here is a xilinx forum thread that discusses reducing the cable speed. They also describe the steps on how to reduce the cable speed. thank you, Jon