jpeyron

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Everything posted by jpeyron

  1. Hi @NeedlessBird, Glad to to hear that changing the Vivado version resolved the SDK driver issue. Thank you for sharing what you had to do to resolve this issue. best regards, Jon
  2. Hi @patelviv, I have moved your thread to a section where more experienced embedded linux engineers look. Here is a non digilent tutorial that might be helpful. best regards, Jon
  3. Hi @michaelgood411, Welcome to the Digilent Forums! I have moved your thread to a section where more experienced embedded linux engineers look. best regards, Jon
  4. jpeyron

    CPR 290-006

    Hi @Sergei, Welcome to the Digilent forums! I believe that the 1:19 Gear Ratio DC Motor/Gearbox has 1 pulse per revolution. Here and here are forum thread that discusses the CPR. best regards, Jon
  5. Hi @Arjun, I typically use standalone applications. I would not have a lot of information on this topic. Here and here are xilinx forum threads where they discuss a similar issues. best regards, Jon
  6. Hi @SGY, Welcome to the Digilent Forums! The Zedboard is a collaboration between a few companies. Due to this situation, there are a two places to look for good documentation. Here is the Digilent resource center for the Zedboard. The Avnet site is zedboard.org . The ZYNQ book was written for the Zedboard and the Zybo Zynq boards. The Zedboard OLED demo is written in Verilog. I would also look at the FPGA4FUN and Asic world for more basic non specific board HDL code. The Zedboard has a ZYNQ processor where some of the components like the DDR and USB UART bridge are tied directly to the Arm Core. These components will not be able to be used in the PL with HDL but can be used in the PS using the ZYNQ processor. I have attached an image that should help with visualizing this. best regards, Jon
  7. Hi @eric_holtzclaw, Welcome to the Digilent Forums! In your Vivado_init.tcl I would first try deleting the < in front of the F: and have the full path to the board files. Next, I would erase the "# test" text and have an empty first line of the file. It may help to make put the board files on the same drive that Vivado is on. I have attached my working .tcl file. Some of the older versions of Vivado i have installed requires a different file name(init.tcl). best regards, Jon init.tcl
  8. Hi @Allan Flippin, The USB UART connector/programming circuit on the Arty works with microblaze allowing you to debug in SDK. If you were wanting to use the JTAG HS2 as an alternative for configuring/debugging and running an application for the Arty in SDK you can do that to. I just made a simple GPIO/uart project using the JTAG HS2/JTAG connector to program the fpga and run the application which worked with one exemption. Using the JTAG HS2 did not facilitate a com port for serial communication. best regards, Jon
  9. jpeyron

    Vivado free for Artix-7?

    Hi @TerryS, Glad to hear you were able to get Vivado downloaded , installed and get through the "blinky" tutorial! Thank you for sharing what you had to do to get this done. best regards, Jon
  10. Hi @Kris Persyn, I'm glad to hear you were able to get the HDMI project up and running. Thank you for sharing what you had to do! best regards, Jon
  11. Hi @M.Mahdi.T, Welcome to the Digilent Forums! We typically do not test the max throughput metric when validating our products. Looking at the AD5933 datasheet here the Pmod IA would be limited to 1 MSPS due to the on board ADC. The main bottleneck for throughput to a host board will be the I2C communication which runs at 400 KHz. Here is a good forum thread for using the Pmod IA with the Raspberry PI with code and hints for use , setup and calibration. Here is the resource center for the Pmod IA which has the Raspberry PI code as well. best regards, Jon
  12. Hi @PG_R, I have connected many different fpga's to my PC through Ethernet using a standard Ethernet cable. I believe a regular ethernet cable will do just fine. The difficult process will be facilitating the ethernet communication. That is why I suggested using the petalinux project linked above. best regards, Jon
  13. Hi @Allan Flippin, Here is the VHDL code for the UART TX from our GPIO demo for the Arty-A7-100T which sets the tx baud rate to 9600. I have not used auto baud detection since typically we dictate the baud rate in our projects. best regards, Jon
  14. Hi @Allan Flippin, If you use the Arty-A7 35T or 100T or the Arty-S7 50T or 25T you can use a HDL(Verilog/VHDL) UART controller to communicate through the USB UART bridge. ZYNQ FPGA's have some of the components on the board tied directly to the Arm processor(PS). The DDR3 and USB UART bridge would be included in these components. With ZYNQ FPGA's you can not use the PL to directly use the USB UART bridge. I have attach an image that is a good reference on the ZYNQ processor. To use the USB UART bridge with the Arty-Z7 20 or Arty-Z7 10 you would need to use the Zynq processor. Here is the getting started with ZYNQ tutorial for the Zybo that can easily be used with the Arty-Z7 . The GSWZ tutorial shows how to use the PS to communicate through the USB UART bridge. Here is the Arty-Z7 , Arty-A7 and Arty-S7 resource centers. best regards, Jon
  15. Hi @hmd, I'm glad to hear that the command which vivado helped you find the path needed to complete the installation. Thank you for sharing what you did. best regards, Jon
  16. Hi @kwilber, Thank you for sharing. This book looks awesome! cheers, Jon
  17. Hi @vttay03, I have not been able to be able to get the Hello world template to work with the QSPI flash with either the Arty-A7 35T or the Arty-A7-100T in Vivado 2018.3. I will keep looking into this issue with Vivado 2018.3. For now I would suggest using Vivado 2017.4. I was able to complete and verify the Hello world template project into the QSPI flash on the Arty-A7-100 using Vivado 2017.4. I attached some screen shots of the programming setting in SDK. Also the offset is 0x003D0900 since the HW platform size is the same as the Nexys 4 DDR which has the same FPGA. best regards, Jon
  18. Hi @hmd, I opened my VM and looked opt/ from the root directory. It has the Xilinx/ directory. I think it would be best to uninstall and re-install Vivado an leave it to default settings. Make sure that you are root while installing Vivado to insure there is no issues with permissions. best regards, Jon
  19. Hi @PG_R, I do not have much experience connecting two FPGA's together through ethernet. Initially I do not see any reason that you would not be able to connecting these boards together through ethernet. I would suggest using the Petalinux project for the Zybo Z7 to facilitate the ethernet. best regards, Jon
  20. jpeyron

    Genesys 2 DDR Constraints

    Hi @SeanS, @JColvin response was also my thoughts based on the screen shot. The color scheme of the MIG page attached looks like ISE. I am glad that you are now able to get the MIG default setting to be pre-set by the board files. best regards, Jon
  21. Hi @hmd, Change directory(CD) to the root directory and run the command s -l there. Its been a little bit since I have played around with Linux in my Virtual machine. I believe the OPT directory is there. Sorry about the mis-information. best regards, Jon
  22. Hi @FPGAMaster, The programming circuit is considered proprietary. I have PM'd you the next step in regards to the programming circuit. best regards, Jon
  23. Hi @Allan Flippin, It's my understanding that there is no current plans on adding access to the memory like for the newer families of FPGA's in Adept 2. I am also not aware of any other application that facilitates that type of interaction with memory. If using the USB UART bridge is a feasible alternative, could you be more specific about your data rate needs for transferring/receiving data to the PC? There are quite a few HDL(VHDL/Verilog) UART Controllers available with a quick google search. We also have projects that transfer data through the USB UART bridge using HDL like the Arty-A7 100T GPIO demo. This older tutorial uses the Microblaze processor and uart lite IP Core that uses the USB UART bridge as well. best regards, Jon
  24. Hi @Allan Flippin, The memory functionality you discuss above for the Nexys 3 is not facilitated for the newer FPGA families like the Artix-7 and ZYNQ. Adept 2 does still allow users to configure newer xilinx FPGA's using .bit files. Adept 2 can be downloaded here along with the Adept 2 reference manual. best regards, Jon
  25. Hi @hmd, 1) Did you install Vivado 2018.3 on a different drive? 2) Was vivado 2018.3 installed at the default path? 3) Please attach a screen shot of the command " ls -l " when in the home/ and the opt/ directory. Also make sure that you are root. best regards, Jon