jpeyron

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Everything posted by jpeyron

  1. jpeyron

    Vivado Bitstream Generation

    Hi @Hunaina, Here is a xilinx forum thread that discusses the Error Labtools 27 3165 End of startup status LOW. They state that "There are two reasons that the voltage could drop, first that it exceeds the capacity of the supply, and second that the sudden increase in current causes the supply to dip briefly and there is not enough bulk bypass capacitance to hold the voltage above the minimum required to retain configuration." 1) What is the spec's for your wal- wart you are using to power the Zedboard? thank you, Jon
  2. jpeyron

    ZYNQ AP transaction error, DAP status f0000021

    Hi @Mukul, 1) Please attach a screen shot of your Vivado block design. 2) Are you using the Digilent board files? 3) why is there a verilog_HW_platform in your Project explore tab of the SDK? cheers, Jon
  3. jpeyron

    ZYBO Z7 LWIP ECHO ETHERNET ISSUE

    Hi @regnon, 1) Yes the Arty-Z7 and the Zybo-Z7 use the same Realtek RTL8211E-VL PHY to implement a 10/100/1000 Ethernet port. 2) The digilent board files should be configuring the ethernet correctly. You should not need to alter the default settings(given you are using the Digilent board files). 3) Are you changing anything in the ZYNQ processor or doing anything different from the getting started with ZYNQ server? 4) Another suggestion would be to try a different Vivado version like Vivado 2017.4 or Vivado 2016.4. The xxxx.4 version of vivado is typically the most stable and bug free. thank you, Jon
  4. jpeyron

    ARTYS7 Rev E Schematic J11

    Hi @atluft, J9 is labeled on the bottom of the Arty-S7 as shown on the screen shot below. J9 is shown on the top of page 6 of the schematic for rev E here. J11 is on the bottom of page 10 of the schematic. Please attach a picture of J11 and J9 if your Arty-S7 rev E is not labeled as shown below. cheers, Jon
  5. jpeyron

    Linux spidev interface to joystick

    Hi @carcher, I moved your thread to a section when more experienced embedded linux engineers look. thank you, Jon
  6. jpeyron

    No thing is appearing at Tera Term !

    Hi @Ahmed Alfadhel, To confirm you were getting uart communication. Then you alter the frequency to 333 MHZ the uart stopped. I would think that changing the frequency could be the issue. I would suggest altering back to the original frequency and then testing the uart. The digilent board files are made to correctly configure the ddr and microblaze among other thing. Why are you changing the frequency? thank you, Jon
  7. jpeyron

    upgrade Vivado 2018.2 tutorial to Vivado 2018.3

    Hi @Jubullu22, I had some issues trying to upgrade this project directly to 2018.3. To get past the vivado issues i had to generate a bitstream using Vivado 2018.2 and then open the project using VIvado 2018.3. Here is the unverified project vivado 2018.3 Nexys A7-DMA-audio demo. thank you, Jon
  8. jpeyron

    pmod wifi

    Hi @harika, I have not ran into the error lock down A303 error before. I did find a refernce to a error lock down A304 on this Xilinx forum thread. 1) I would suggest not having the Linux files on the SD card. 2) Here is the zedboard reference manual. What mode setting do you have on the Zedboard (page 28 and attached screen shot). 3) In regards to the Zynq processor make sure you are using the digilent board files. The board files become the default setting for the ZYNQ processor when you are running block automation. I would suggest not altering the default settings, until you have a working project. Then I would worry about optimizing the project. thank you, Jon
  9. jpeyron

    Hi Everyone!

    Hi @SethK, Welcome to the Digilent Forums! cheers, Jon
  10. jpeyron

    Simple HDMI pass through with NexysVideo

    Hi @neocsc, Here is a verified Nexys Video HDMI project updated from Vivado 2016.4 to Vivado 2017.4. You should be able to find the updated project in the proj folder . Here is a GitHub project done in HDL using the clocking wizard, DVI2RGB and RGB2DVI IP Cores for another FPGA. Here is a unverified Nexys Video Vivado 2017.4 HDMI pass through project made from the linked Github project. In the next few days I should have the bandwidth to verify this project. thank you, Jon
  11. jpeyron

    Nexys 3 Pmod Nav Problem

    Hi @NiLo, I have not found any verilog projects with the PmodNAV. I did find a FPGA-Based Real-Time SLAM paper that might be helpful. cheers, Jon
  12. jpeyron

    Nexys 3 Pmod Nav Problem

    Hi @NiLo, Here is the Vivado Library which has IP cores for most of our Pmods including the PmodNAV. I would look at our driver to see how we solved this. I would look at the following functions in the PmodNAV.c. I would also look at the following functions in main.c thank you, Jon
  13. jpeyron

    Vivado Bitstream Generation

    Hi @Hunaina, Here is a xilinx forum thread that discusses reducing the cable speed. They also describe the steps on how to reduce the cable speed. thank you, Jon
  14. jpeyron

    ZYBO Z7 LWIP ECHO ETHERNET ISSUE

    Hi @regnon, 1) What TCP/IPv4 IP address and subnet mask are you using on the PC? 2) can you include a screen shot of the PuTTY setting you are using to connect to the Ethernet on the Zybo-Z7? thank you, Jon
  15. jpeyron

    ZYBO Z7 LWIP ECHO ETHERNET ISSUE

    Hi @regnon, 1) What OS is your PC 2) Have you verified that the ethernet cable is working? 3) please attach screen shots of the com port and ethernet connections with a serial terminal like Tera Term or PuTTY. 4) Another way to verify the ethernet would be to load a pre-built verified petalinux platform for the Zybo-Z7. thank you, Jon
  16. Hi @varunb, It looks like you have received help on your other post here . thank you, Jon
  17. jpeyron

    Simple HDMI pass through with NexysVideo

    Hi @neocsc, I believe you should be using the hdmi_rx_hpa from the master xdc for the Nexys Video here. #set_property -dict { PACKAGE_PIN AB12 IOSTANDARD LVCMOS25 } [get_ports { hdmi_rx_hpa }]; #IO_L7N_T1_13 Sch=hdmi_rx_hpa thank you, Jon
  18. jpeyron

    Failure : IP Integrator tutorial with Vivado 2014.4

    Hi @Danny Armstrong, Unfortunately we do not have a 32 bit PC available to load Vivado 2014.4 on to. Please include step by step screen shots of your process so we can better assist in getting this version of Vivado up and running. Please include your block design and wrapper/xdc file and your sdk code. thank you, Jon
  19. jpeyron

    Zybo Z7-20 Pcam 5C Demo with YCbCr422/RGB565

    Hi @Takeshi, You might want to look at the Pmod OLEDrgb driver/libraries since it uses the RGB565 format. Here is a forum thread discussing the ADV7611 along with this user guide and this linux driver. thank you, Jon
  20. jpeyron

    Board Path Respositary path

    Hi @SivaNageswara Rao, Welcome to the Digilent Forums! I moved your post to a section dealing with FPGA's. The path you added in the tcl script when following the Board file tutorial here is not usable by Vivado. There can not be spaces in the path-name. Please attach you vivado_init.tcl script. thank you, Jon
  21. jpeyron

    multiple SPI based DAC connection from single PMOD

    Hi @amitlwaghmare, 1) What DAC are you using? 2) If possible please attach your block design/wrapper/xdc and SDK code(if applicable) 3) I believe you will need to alter your initialization function to configure each DAC and to use multiple DAC's in this way. 4) Here is an example of the changes needed to be made Expanding the Number of DAC Outputs on the ADuC8xx and ADuC702x Families. thank you, Jon
  22. jpeyron

    pmod wifi

    Hi @harika, 1) The Pmod WIFI facilitates the connection to a WIFI Network. We have provide a few example for usage. a) You should see the Pmod WIFI connecting through the serial terminal text. 2) I haven't tried using a WIFI Hotspot but i do not see a reason why you can not use the hotspot. If the Pmod WiFI connects to your mobile hotspot then there shoulds not be an issue. thank you, Jon
  23. jpeyron

    Simple HDMI pass through with NexysVideo

    Hi @neocsc, Please attach a screen shot of the error. Not all timing errors will break a project. 1) Are you still able to generate a bitstream or does the timing error force the bitstream generation to stop? 2) If you are able to generate a bitstream please export the hardware(include bitstream), launch sdk and import application. Then program the fpga and run as ->launch on hardware(system debugger). 3) If so does the project make a serial terminal menu? $) If so does the project generate a HDMI pass through along with a pre-generated image? thank you, Jon
  24. jpeyron

    high speed ADC with zedboard

    Hi @devriese.wouter, Here is the Zedboard's reference manual which goes into detail that two of the Pmods, JC1 and JD1, are aligned in a dual configuration and have their I/O routed differentially to support LVDS running at 525Mbs. The on board XADC does 2 channels, 12 bits at 1 MSPS which is described the 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide. Also the Pmod AD1 is a 2 channel, 12 bit, 1 MSPS ADC as well. I would suggest using the Zedboard's on-board XADC first and make sure this will work for you. If so them I would then look into using the Pmod AD1 as well. You can use the Pmod AD1 on any of the PL Pmod Ports. thank you, Jon
  25. Hi @Raff, Here is the Adept 2 link, sorry about that. thank you, Jon