jpeyron

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Everything posted by jpeyron

  1. Hi @aadgl, Unfortunately, we do not have an example of interacting with the MIG through VHDL/Verilog. Here is a forum thread that discusses using the DDR3 on the Arty not through Microblaze. @D@n includes some tutorials and code that should be useful for your situation. best regards, Jon
  2. Hi @billium, We have passed on your suggestion for a more clear error code for unsupported FPGA's. I know that it might be a hassle but i believe you can used different email addresses to set up different accounts to be able to use ISE 14.7 webpack on different PC's. best regards, Jon
  3. Hi @Kampi, Either would be a good reference with the VDMA IP Core. Agree, for sending video out through the HDMI the HDMI-OUT demo would be a better reference.
  4. Hi @nitish.moheeputh, After powering down the Zybo Z7 the FPGA/ZYNQ configuration in JTAG mode from either the HW manager or SDK will be lost. You will need to create a BOOT.BIN file as described in this older tutorial for the Zedboard here and load it into either the QSPI Flash or and SD card in the root file. The mode jumper JP5 will need to be appropriately set as shown in the reference manual here. best regards, Jon
  5. Hi @daeroro, The Pmod CAN IP core does not use the interrupts. How many Pmod CAN's do you have. If you have two Pmod CAN's are you able to run the loop back demo? The data sheet here will help you configure the Pmod CAN. best regards, Jon
  6. jpeyron

    TCS34725 Basys3 VHDL

    Hi @kmesne, Typically the top file contains the signals needed as input/output to the FPGA board. Since you are taking data into the FPGA board for this sensor using I2C , then you would need to have these signals in the top file as well as being constrained. Here is a non-digilent tutorial about using I2C with VHDL that should be helpful. best regards, Jon
  7. jpeyron

    xadc_zynq

    Hi @revathi, Here and here are a few forum threads that have SDK code using the xadc and a zynq processor that should be helpful for getting usable data. Also could you attach a link to the zynq board you are using. Have you tried other aux channels? best regards, Jon
  8. Hi @billium, I looked more for the error you are getting and found a forum thread here that had the same issue. I believe that the spartan 6 fpga on your non-digilent board is not one of the supported spartan 6's. iMPACT would be your only option in this case. best regards, Jon
  9. Hi @Sami Malik, We have not altered the BRAM IP core to move more that 32 bits. Please attach a screen shot of your block design altered to work with more than 32 bits to see what you are altering. In regards to DOUT. DOUT is the output pin from the Memory generator to the DIN pin on the multiple bits IP Core. best regards, Jon
  10. Hi @ray perry, Glad to hear that you were able to find a usable sketch and figured out what you needed to adjust to get the SD card working on the WF32. Thank you for sharing what you did to get the SD card working. best regards, Jon
  11. Hi @Kampi, I think that the VDMA addresses could be incorrect as shown by the print out. I would suggest looking at the HDMI IN demo as a reference. best regards, Jon
  12. Hi @billium, I would say to check for the log file here: /tmp/debugerc.log If there is no log file create a file there and re-run adept 2 and see if it writes the to the log file. Also I was under the impression that ISE 14.7 webpack edition is available at not cost which should allow you to configure the FPGA through iMPACT. best regards, Jon
  13. Hi @Pooldawg, Welcome to the Digilent forums! Digilent typically handles any hardware issues. NetFPGA wiki handles setup, software, configuration and applications for the Netfpga development boards. The NetFPGA wiki is more familiar and experienced using these development boards and would be better suited to answer your question. You will need to register with them here. It may take a few business day to get approved. best regards, Jon
  14. Hi @Hamza Muneer, Welcome to the Digilent forums! Unfortunately, We did not have the bandwidth to facilitate the additional functions for the newer fpga families in Adept 2. I would suggest configuring the Arty S7 FPGA using the Arty S7 General I/O Demo to validate the GPIO . best regards, Jon
  15. Hi @Ahmed darwish, What FPGA development board are you using? Please attach your hdl and ucf files. best regards, Jon
  16. Hi @bhall, Here is the How To Store Your SDK Project in SPI Flash. The beginning of the tutorial describes ways to reduce configuration time. best regards, Jon
  17. jpeyron

    Zybo Led Project

    Hi @selami, Can you please attach a link to the project you are referring to. Here is the resource center for the Zybo. Or are you referring to the Zybo-Z7. best regards, Jon
  18. Hi @dxb, Welcome to the Digilent Forums! Here is the resource center for the retired Pmod RF1. We have two different projects using a microcontroller on the Pmod RF1 but none for an FPGA using Verilog. We currently do not have the bandwidth to create a verilog project for the Pmod RF1. I would suggest using the microcontroller projects, the data sheet and the reference manual to help you configure the Pmod RF1. best regards, Jon
  19. Hi @ray perry, The Digilent Core here has a SD card sketch usable with the WF32. I have attached a screen shot of the sketch. best regards, Jon
  20. Hi @greatqueentomato, Welcome to the Digilent forums! best regards, Jon
  21. Hi @hearos, I will have some bandwidth to make an sd card, pmod OLEDrgb, nexys 4 ddr, vivado 2018.3 project on Monday. best regards, Jon
  22. Hi @Alonso, I have not simulated the SRAM to DDR component but I have used it in multiple projects. Here is the legacy tutorial getting started with microblaze that uses the SRAM to DDR component. best regards, Jon
  23. Hi @daeroro, Sorry for the late response, we were out of the office some of last week and this week. Please attach a screen shot of your vivado block design along with your sdk code. What mode are you using I.E. loop back or normal? best regards, Jon
  24. Hi @billium, To clarify, ruffly a year ago you were able to configure you XC6SLX FPGA through iMPACT and Adept 2 using Debian 9. You have upgraded to Debian 10 and now iMPACT and Adept 2 are not able to configure the XC6SLX FPGA and get an unrecognized error code. Using the command "djtgcfg enum" for Adept 2 what is the terminal text response? I would like to add error logging in adept 2: 1. Add the ability to enable error logging by setting the "ADEPT_RT_LOGDETAIL" environment variable to a value greater than or equal to '1'. Presently all values greater than '0' result in the same output to the log file. Future revision may include the ability to output additional debug information by setting different error levels. 2. Added the ability to specify the path to the error log file by setting the "ADEPT_RT_LOGFILE" environment variable. If error logging is enabled and the path has been specified then any errors that occur will be logged to the specified file. If error logging is enabled and the "ADEPT_RT_LOGFILE" environment variable has not been set then any errors that occur will be logged to a file named "DebugErc.log", which will be created under the application's current working directory. Please attach the DebugErc.log when attempting to connect to the FPGA. best regards, Jon
  25. Hi @vttay03, Glad to hear that you were able to get past this issue. Thank you for sharing what you had to do. Here is a xilinx forum that explains more about global synthesis instead of OOC synthesis. cheers, Jon