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Everything posted by jpeyron

  1. jpeyron conflict with libftd2xx-devel package

    Hi @clonest1ck, We reached out to one of our design engineers about this issue. Their department would not have the bandwidth for some time to make a version of adept 2 runtime where the libftd2xx is a dependency. They suggested installing manually from the tar.gz. thank you, Jon
  2. jpeyron

    Vivado 2018.3 can't find Digilent board files

    Hi @CaptIgmu, Glad to hear you were able to get Vivado 2018.3 working on Ubuntu 18.04 LTS! Thank you for sharing what you needed to do to use the Digilent board files. cheers, Jon
  3. jpeyron

    booting from sd card

    Hi @Michael P, Here is the Nexys Video reference manual. In section 2.3 USB Host and MicroSD Programming on page 9 it described how to use an sd card to configure the FPGA. The steps are as follows: 1. Format the storage device (pen drive or microSD card) with a FAT32 file system. 2. Place a single .bit configuration file in the root directory of the storage device. 3. Attach the storage device to the Nexys Video. 4. Set the JP4 Programming Mode jumper on the Nexys Video to "USB/SD". 5. Select the desired storage device using JP3. 6. Push the PROG button or power-cycle the Nexys Video. thank you, Jon
  4. jpeyron

    booting from sd card

    Hi @Michael P, Here is a Xilinx forum thread that discusses trying to boot from the SD card with a Artix-7 FPGA. Here is the How To Store Your SDK Project in SPI Flash tutorial configuring the QSPI FLASH to boot a project on power up. cheers, Jon
  5. jpeyron

    Software for loading and creating C file

    Hi @prashant, 1) The memory error makes me think that the mode Jumper JP4 set to SD. The mode Jumper JP4 should be set to JTAG. 2) Do you have the board files correctly installed as described in this tutorial. thank you, Jon
  6. Hi @Ted, Here is a non-digilent image filter project that uses the Zybo-Z7 that look to be helpful for your project. thank you, Jon
  7. jpeyron


    Hi @Freshwell, Welcome to the Digilent Forums! 1) Make sure that you are using the Digilent board files. 2) Make sure you are using the Digilent master XDC. Here is the master XDC for the Genesys 2. The master XDC individually constrains each pin including the voltage. For example: #set_property -dict { PACKAGE_PIN E18 IOSTANDARD LVCMOS12 } [get_ports { btnc }]; #IO_25_17 Sch=btnc this sets the pin E18 to the IO Standard LVCMOS12 which sets the pins voltage to 1.2 V. In the schematic here on page 12 you will see that E18 is connected to bank 17. Bank 17 is not set to 3.3V. 3) Please include your HDL and or a screen shot of your Block design, wrapper and xdc file so we can better help with this issue. 4) Please also include a screen shot of the errors you are getting. thank you, Jon PS, Since many of the pins use a different voltage not 3V3 I do not believe you want to make a blanket constrain like set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] Here is the Vivado Design Suite User Guide Using Constraints and Constraints Guide that will explain how to correctly use the XDC in more detail.
  8. jpeyron

    GPS driver question.

    Hi @StefanOR, Here is a forum thread that discusses using the that might be helpful for your project. I believe that the GPS_setUpdateRate(&GPS, 1000); //Sets the frequency that the PmodGPS sends sentences. and an interrupt is sent every 8 bytes GPS_intHandler(PmodGPS *InstancePtr, u32 Event, unsigned int EventData) sets the InstancePtr->ping = TRUE; The PmodGPS.c, PmodGPS.h and main.c will be the files to look through. thank you, Jon
  9. jpeyron

    Change of Clock setting on ZYBO

    Hi @Nan-Sheng, Please give more details about your project. I.E. HDL or ZYNQ processor? IP Cores? external peripherals? In section 12 Clock Sources of the reference manual here it describes the clocking options. If you are using HDL(VHDL/Verilog) you can use the clocking wizard to generate your desired frequencies. If you are using the ZYNQ processor you can add an addition clock in the PL that will be accessible in the block design. thank you, Jon
  10. jpeyron

    Pmod DA3 clocking

    Hi @Ahmed Alfadhel, Looking at the Datasheet for the AD5541A here.The AD5541A operates at clock rates of up to 50 MHz and is compatible with SPI, QSPI, MICROWIRE, and DSP interface standards. I believe the highest frequency would be 50 MHZ for the ext_spi_clk. Its my understanding that we use the MIG_7series/ui_clk :83 MHz clock due to issues relating to the MIG/DDR. I would also suggest looking at the AXI Quad SPI v3.2 LogiCORE IP Product Guide. thank you, Jon
  11. jpeyron

    Question about adding Pmod

    Hi @Mingfei, Welcome to the Digilent forums! I would suggest starting with a fresh non-altered Arty-Z7-20 HDMI-OUT project. Once you have opened the Arty-Z7-20 HDMI-OUT project in Vivado 2018.2 then: 1) Download the Vivado library. 2) In Vivado 2018.2 click on IP in project setting select repository and add the path to the vivado library. 3) Then right click on the pmod port of your choice and select the Pmod AD5. 4) Double click into the zynq processor select pl clocks and add a 50 MHz clock and select OK. 5) Connect the 50 MHz clock to the ext_spi_clk pin on the Pmod AD5 then run connection automation. 6) Right click on the wrapper and update the hierarchy. 7) generate bitstream cheers, Jon
  12. jpeyron

    How to use Pmod Grove RTC inside the PYNQ project

    Hi @Mahdi, I found this GitHub project using the i2c.h and the DS1307 here that should be helpful. thank you, Jon
  13. jpeyron

    Software for loading and creating C file

    Hi @prashant, Here is the HDMI-IN demo. The SDK portion of the project which is done in C is here for the Arty-Z7-20 and here for the Arty-Z7-10. Please follow the readme for specific Arty-Z7 you have. The Arty-Z7-10 or the Arty-Z7-20 to use the HDMI-In project. thank you, Jon
  14. jpeyron

    Vivado 2018.3 can't find Digilent board files

    Hi @CaptIgmu, Please download Adept 2 here. Please use the terminal command : # djtgcfg enum Here is a forum thread that discusses this situation with linux OS that might be helpful. thank you, Jon
  15. jpeyron

    Pmod wifi

    Hi @kavya@iiitn, Sorry for any confusion. 1) The jumpers I pointed out are above the Digilent logo on the Zedboard. 2) On the Zedboard please have MIO[2] -MIO[6] jumpers connected to ground. 3) This will set the mode to JTAG. 4) In your attached picture MIO[5] AND MIO[4] are not connected to ground(set to 0). I would also suggest going through the tutorials on the zedboard resource center as well as looking at the ZYNQ book. thank you, Jon
  16. jpeyron

    UDP IP Ethernet on Nexys Video from PC to FPGA

    Hi @hello.parth, The Ethernet IP cores use the AXI BUS. You would need to implement the AXI BUS communication to interact with the Ethernet IP Cores. This is not an easy task. You do not need to use Microblaze or the Ethernet IP Cores to use the ethernet on the Nexys Video. Here is a community members( @hamster) VHDL GigabitTX project using the Nexys Video. thank you, Jon
  17. jpeyron

    Pmod BT2 is not turning on.

    Hi @Abdul Qayyum, The RN-42(IC) uses 3.3 logic as shown in the resource center for the Pmod BT2. Here is the home page for the RN-42 here. 1) On page 48 of the Bluetooth Data Module Command Reference & Advanced Information User’s Guide is states that "When using a 5.0-V DC input, GPIO pins require a voltage divider. A good choice is a 10 KΩ series with 20 K to ground. The GPIO pins are 0 - 3.3 V DC, not 5-V tolerant." The Pmod BT2 could have been damaged due to the 5V. thank you, Jon
  18. jpeyron

    BASYS3 USB not recognized

    Hi @engvlad, Glad to hear you are able to use the Basys 3 after changing out the USB cable. Here is the resource center for the Basys 3 if you havent seen it yet. cheers, Jon PS: Welcome to the Digilent forums!
  19. jpeyron

    SD card partitioned for booting linux

    Hi @Ram, Here is an instructable for installing Petalinux that describes having two partitions. Here is a link on how to partition the SD card in Windows 10. thank you, Jon
  20. jpeyron

    booting linux on zynq with SD card

    Hi @Arjun, I moved this thread to a sub-section where more experienced embedded linux engineers look. cheers, Jon
  21. jpeyron

    Zybo z7-10/20 Compatible Software

    Hi @sidesantis01, Yes, the Vivado webpack works with the Zybo-Z7-10 and Zybo-Z7-20 development board. Here is the resource center for the Zybo Z7. What type of project are you prototyping? cheers, Jon
  22. jpeyron

    Pmod wifi

    HI @kavya@iiitn, The video can be used for the Zedboard. The Vivado block design portion is for an Arty-A7(microblaze) so that will be different. For the Vivado portion of the project: 1) Make sure that you are using the Digilent board files as described in this tutorial and have added the Vivado Library to the IP repository. 2) Use the default settings(Digilent board files) for the ZYNQ processor when doing block automation. 3) The GPIO and Pmod WIFI IP Cores should be handled similar to the video. Once you are finish with the Block design creating a wrapper and generating a bitstream will be the same as the video. For the SDK portion of the video 1) Everything should be the same as the video. The main thing I see on the Zedboard setting is that the mode jumpers have the Zedboard set to SD. The Zedboard mode should be set to JTAG. The settings table screen shot is attached below and can be found in the reference manual on page 28. All of the mode jumpers should be tied to ground. thank you, Jon
  23. Hi @Ted, Here is the WIKI for the Zybo-Z7-20-Pcam-5C project. I did not see an option to capture raw images. The option e: e - Write a Register inside the Image Sensor This option allows you to write a value to any register inside the Image sensor over the OmniVision SCCB interface. You will need to refer to the OV5640 datasheet for information on the register map. This option is very useful for exploring the features of the image sensor. I would look at the Data sheet on the Pcam-5C resource center here as well as other libraries like this arduino library as a reference on how to facilitate different features. thank you, Jon
  24. jpeyron

    Zybo-Z7-20-pcam-5c demo project with vivado 2018.3

    Hi @kenichisasaki, We do not have the bandwidth to update our Vivado content on every 201X.X release. Unfortunately, Vivado projects are tied to the 201X.X release it was made with or updated to. Here is a forum thread that discusses this error with the Zybo-Z7-20-PCAM-5C demo.I would suggest downloading Vivado 2018.2 to use this demo. You can have multiple versions of Vivado downloaded to the same PC. thank you, Jon
  25. jpeyron

    ZYNQ AP transaction error, DAP status f0000021

    Hi @Mukul, Glad to hear the board is working correctly! Thank you for sharing what the issue was. cheers, Jon