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Everything posted by jpeyron

  1. Hi @Sami Malik, I reached out to a co-worker about this thread and they pointed out that you are writing into the controllers register space, not the brams memory space. you are not accessing the 0,1,2,3 addresses of the bram by reading it from rtl based on how you have it set up. They also suggested that you should try to import an example from system.mss to get an idea of how xilinx uses the driver as well. best regards, Jon
  2. Hi @nakedtofu, Welcome to the Digilent Forums! I would suggest using the version of vivado that this project was made for and is verified to work with. Upgrading projects to newer versions of Vivado can become a non-trivial task. IP Cores can have changes that require configuration alterations to other IP Cores for them to interact correctly. We currently do not have an eta for when we will be upgrading this project to a newer version of Vivado. If you are going to continue in the newer version of vivado this might be a long road ahead of you before having a verified project. best regards, Jon
  3. jpeyron

    AXI4 and Vivado ILA

    Hi @Sduru, Here and here are forum threads that should be helpful with fixing the IP error you are experiencing. best regards, Jon
  4. Hi @JeffJ, Unfortunately we are not aware of an easy way to update the firmware. I will pass on your suggestion for different fonts to our content team. best regards, Jon
  5. Hi @nitish.moheeputh, Here is the resource center for the Zybo Z7 which has a link to the schematic, the master xdc and the Zybo Z7 HDMI Demo. best regards, Jon
  6. jpeyron

    Wifi audio hub

    Hi @chaminda12001, This an interesting and very complex project that unfortunately goes beyond the scope of the forums. If I were attempting this task I would probably be using a zynq development board with the Pmod ESP32 IP core with the Petalinux platform. Beyond this I would not have enough experience to give usable advice. best regards, Jon
  7. Hi @Thiago, I have not extracted a netlist from an FPGA. I did find a non digilent paper that might be helpful for your needs. Here is an older xilinx forum thread that discusses this as well. best regards, Jon
  8. Hi @SeanS, I heard back from our more experience engineers and they responded that if the MIG design guidelines are met, the interface is considered verified. As discussed in this xilinx forum thread. The DQS signals are strobe/clock signals and due to the particularities of the DDR3 interface they are delayed internally during calibration. No static timing check is necessary. For a final check you could create a MIG design for a Xilinx dev board and see if the same warning is given there. If yes, then it is expected behavior. best regards, Jon
  9. Hi @Thiago, Welcome to the digilent Forums! To clarify , you are wanting to copy the bit/elf file on an existing configured Arty A7 35T to your PC. best regards, Jon
  10. Hi @cramcram, I moved your thread to a section closer to your questions topic. What OS are you using? best regards, Jon
  11. Hi @rbttech, Here is a forum thread that should be helpful for getting the Cool runner II working with Adept. The caveat that we're not certain since we don't have that particular OS to be able to readily test this ourselves. best regards, Jon
  12. Hi @SeanS, We reached out to one of our co-workers about this thread and they believe that this warning can be ignored. We have also reached out to more experienced engineers about this thread as well. best regards, Jon
  13. Hi, Welcome to the Digilent Forums! What OS is your PC? Are you dual booting or using a virtual machine? Are you able to see the Zybo Z7 10 development board using lsusb in linux or in the device manager in windows? Please download Adept 2 here. Does Adept 2 recognize the Zybo-Z7-10? best regards, Jon
  14. Hi @Bartowski, I have sent you a PM about this. best regards, Jon
  15. Hi @peerlesspalmer, Welcome to the Digilent forums. I moved your thread to a section where more experience AD2/WaveForms engineers look. best regards, Jon
  16. jpeyron

    Wifi audio hub

    Hi @chaminda12001, Welcome to the digilent forums! Sounds like an interesting project. Please be more specific about your project needs. best regards, Jon
  17. Hi @hearos, Here is a completed and verified Vivado 2018.3 Nexys 4 DDR SD card and OLEDrgb on JA project. The has not been altered to work with the OLEDrgb but the HW platform includes the needed libraries. I also added the the below code to the OLEDrgb.h file. You will need to incorporate the main.c from the OLEDrgb example into the on the top: #ifdef __cplusplus extern "C" { #endif and this to the end of it: #ifdef __cplusplus } #endif so the code will work with C++. best regards, Jon
  18. Hi @aadgl, Unfortunately, we do not have an example of interacting with the MIG through VHDL/Verilog. Here is a forum thread that discusses using the DDR3 on the Arty not through Microblaze. @D@n includes some tutorials and code that should be useful for your situation. best regards, Jon
  19. Hi @billium, We have passed on your suggestion for a more clear error code for unsupported FPGA's. I know that it might be a hassle but i believe you can used different email addresses to set up different accounts to be able to use ISE 14.7 webpack on different PC's. best regards, Jon
  20. Hi @Kampi, Either would be a good reference with the VDMA IP Core. Agree, for sending video out through the HDMI the HDMI-OUT demo would be a better reference.
  21. Hi @nitish.moheeputh, After powering down the Zybo Z7 the FPGA/ZYNQ configuration in JTAG mode from either the HW manager or SDK will be lost. You will need to create a BOOT.BIN file as described in this older tutorial for the Zedboard here and load it into either the QSPI Flash or and SD card in the root file. The mode jumper JP5 will need to be appropriately set as shown in the reference manual here. best regards, Jon
  22. Hi @daeroro, The Pmod CAN IP core does not use the interrupts. How many Pmod CAN's do you have. If you have two Pmod CAN's are you able to run the loop back demo? The data sheet here will help you configure the Pmod CAN. best regards, Jon
  23. jpeyron

    TCS34725 Basys3 VHDL

    Hi @kmesne, Typically the top file contains the signals needed as input/output to the FPGA board. Since you are taking data into the FPGA board for this sensor using I2C , then you would need to have these signals in the top file as well as being constrained. Here is a non-digilent tutorial about using I2C with VHDL that should be helpful. best regards, Jon
  24. jpeyron


    Hi @revathi, Here and here are a few forum threads that have SDK code using the xadc and a zynq processor that should be helpful for getting usable data. Also could you attach a link to the zynq board you are using. Have you tried other aux channels? best regards, Jon
  25. Hi @billium, I looked more for the error you are getting and found a forum thread here that had the same issue. I believe that the spartan 6 fpga on your non-digilent board is not one of the supported spartan 6's. iMPACT would be your only option in this case. best regards, Jon