jpeyron

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Everything posted by jpeyron

  1. Hi @CaptIgmu, Signal names that imply direction are from the point-of-view of the DTE (Data Terminal Equipment), in this case the PC. The input and output signals names are in reference to the PC. When installing Vivado on a linux OS the cable drivers are not automatically installed. 1) Here is a xilinx AR showing how install the xilinx/digilent cable drivers. If you have not already. Make sure to be root. 2) Make sure that you have added yourself to the dialout group. Here is a forum thread that shows how to add yourself to the dialout group. 3) Please download Adept 2 here. a) Use Adept 2 from the command line with the command "djtgcfg enum" . What is the terminal text response? 4) Were you root when you installed Vivado? thank you, Jon
  2. Hi @Sameer120, I have reached out to more experienced engineers about this thread. In the mean time can you post the errors you are getting. thank you, Jon
  3. Hi @TeslaCrytpo, Unfortunately, we do not have a 3D step file for the Cora Z7 development board. We can take caliper measurements if you would like. What specific information were you looking for? thank you, Jon
  4. jpeyron

    Pmod DA3 clocking

    Hi @Ahmed Alfadhel, I reached out to our content team about the default settings and how to change them for the generic SPI IP Core. To change the transaction width you will need to edit the DA3 IP in the IP Packager. Once that's open, double clicking on the SPI XCI in the sources pane will open it's customization wizard. The "Transaction Width" drop down can be set to 16 instead of 8. Click OK, merge changes to sources in the IP Packager, then Repackage the IP and close the packager. Update IPs in the host project and carry on as normal with the Pmod IP. Default settings are in the attached image - They created a default SPI IP using the generator and edited it in IP packager to get this screenshot. They do not know the effects changing C_NUM_TRANSFER_BITS would have on the drivers. If changes to the drivers are necessary, if changes are need to be made they expect that only the XSpi_Config instance in the Pmod's .c driver file would need to be changed. They believe that the asynchronous clock setting only really needs to be used when ext_spi_clk is not derived from the same clock source as the axi clock. If the Pmod IP guide is followed, the setting might be able to be disabled just fine, since both clocks will come from the same clocking wizard or MIG. Their best guess is that the main use case for the Async clock is for when the AXI Quad SPI is configured as a slave to a SPI master off of the board - all of the Pmod IPs use master mode SPI. thank you, Jon
  5. Hi @Blake, I reached out to @BogdanVanca. He said that he will try to make something in the next few days. thank you, Jon
  6. jpeyron

    scanf timeout on ARTY

    Hi @emfries, Here is a xilinx thread that discusses using the usb uart bridge. You should also be able to find an example as discussed in this thread. thank you,
  7. jpeyron

    ─░nappropriate topic

    Hi @kmesne, That sounds like an interesting project. 1) The Pmod Color is a color sensor module with the ability to sense red, green, blue and clear light. 2) Here is the Vivado library. We have an IP Core for the Pmod Color. Here is the Pmod Color's resource center. 3) Here is the resource center for the Basys 3. Please go through the tutorials which will help you install the board files and use the Pmod Color with the Microblaze Processor. The basys 3 board files also make using the buttons with the Microblaze Processor easy as well. thank you, Jon
  8. Hi @Korken, I sent you a PM about this. thank you, Jon
  9. Hi @Shiro, Glad to hear you were able to get your custom IP going. Thank you for sharing what changes you had to make to resolve the multiple driver issue. cheers, Jon
  10. Hi @lkamp, I have sent you a PM about this. thank you, Jon
  11. Hi @enriqeat, 1) can you be more specific on where are you trying to read data from. I.E. usb uart bridge, BRAM, Ethernet, DDR3. I would guess you are trying to read data entered into a serial terminal from a PC using the usb uart bridge. Here is a xilinx thread that discusses using the usb uart bridge. You should also be able to find an example as discussed in this thread. thank you, Jon
  12. Hi @hello.parth, Unfortunately, We do not have the bandwidth to create a HDL ethernet receive from PC to FPGA project. I did find some GitHub projects here and a project in our project vault here that might be helpful thank you, Jon
  13. Hi @dfergenson, Thank you for your suggestions. It is my understanding Digilent has separate informational documents the XDC, Schematic and Reference Manual instead of having all information for a development board in the Reference Manual. I will pass on your suggestion to our content team. thank you, Jon
  14. jpeyron

    Pmod DA3 clocking

    Hi @Ahmed Alfadhel, We have not had the bandwidth to create an IP core for the PmodDA3 as mentioned when I posted the generic SPI IP core Named PmodDA3. This IP core facilitates the usage of the pmod ports along with constraints so as all you should have to do is alter the PmodDA3.c PmodDA3.h and create a main.c. The PmodDA3_main.c is not validated. It would be the first draft when starting to create the custom functions needed to send desired output. thank you, Jon
  15. jpeyron

    Pmod DA3 clocking

    Hi @Ahmed Alfadhel, In the testperiph.c the DemoInitialize() needs to be at the top of main. You need to have a function prototype for DemoInitialize() as well. I would also suggest making your main.c easier to use. Something similar to the attached pmodda3_main.c below. You will need to create the function DA3_WritePhysicalValue. Use the PmodDA1.c and PmodDA1.h as reference. thank you, Jon pmodda3_main.c
  16. Hi @prashant, 1) From you earlier post you stated that you connected the Ethernet? LD8 and LD9 are tied to the Ethernet connection. LD8 and LD9's behavior sounds normal. 2) The demo link above that you appear to be using HDMI IN does not include Ethernet. The HDMI IN demo does not work with Ethernet. 3) Are you able to create a new project and select the corresponding Arty-Z7 version you have in the boards tab? thank you, Jon
  17. jpeyron

    Pmod DA3 clocking

    Hi @Ahmed Alfadhel, Can you please attach the main.c, PmodDA3.c and PmodDA3.h you are using. thank you, Jon
  18. Hi @rocky11, I have sent you a pm about this. thank you, Jon
  19. HI @JMegaffin, I do not see an issue electrically with using a PS/2 splitter. I know the firmware is set up to interact with PS/2 mice and PS/2 keyboards individually. We haven't tried a splitter as of yet, but do not see any issue. Please let us know if you run into issues. cheers, Jon
  20. Hi @Shiro, Here and here are xilinx forum thread that discusses the multiple driver issue when making a custom IP. Here and here are a few ZYNQ tutorials that will help you with making a custom IP. thank you, Jon
  21. Hi @Freshwell, Please try the Genesys 2-OLED demo. Do you get the same results? thank you, Jon
  22. Hi @darin, To clarify, You set the ADEPT_RT_LOGDETAIL to 1 but the DebugErc.log was not created? thank you, Jon
  23. jpeyron

    Pmod DA3 clocking

    Hi @Ahmed Alfadhel, @kwilber is correct. I heard back from our content team. My guess was incorrect. We are using AXI4 Lite so it's definitely not XIP mode, since there is a "MODELPARAM_VALUE.C_XIP_MODE" parameter in the XCI files that is set to 0. They are under the understanding that we are using Legacy Mode . thank yo,u Jon
  24. Hi @gummadi Teja, This is the Nexys 4 DDR Spectral Sources Demo which has FFT source code for the project(also linked above). thank you, Jon
  25. Hi @Thara, I have moved your thread to a section where more experience AD2/Waveforms engineers look. thank you, Jon