jpeyron

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Everything posted by jpeyron

  1. Hi @watmes, 1) Please measure with a DMM the voltage on the capacitor: either C180 - It should be 3.3V. 2) Sorry if my question was confusing. By externally powered I was referring to a 5V power adapter. 3) Are you using a standard USB port or a USB HUB? best regards, Jon
  2. Hi @Billel, Here is a forum that discusses the Vivado System Generator. I believe here is a list of the board available by MathWorks for Simulink. You would need to talk to MathWorks about adding these boards or customize your own board. best regards, Jon
  3. Hi @watmes, Welcome to the Digilent Forums! 1) Please measure with a DMM the voltage on the capacitor: C178 - It should be 5V. 1) I would also try cleaning the power switch while the Nexys 4 DDR unplugged. The contacts on the switch could have some build up and are not getting a good connection. Here is a site that discusses contact cleaner and or compresses air. 2) Have you tried powering the Nexys 4 DDR externally? best regards, Jon
  4. Hi @dry, Welcome to the Digilent Forums. 1) Please download the Adept 2. 2) Use Adept 2 from the command line with the command "djtgcfg enum" . What is the terminal text response? 3) Here is the reference manual for the spartan 3. What mode is the Spartan 3 set to? 4) Here is the resource center for the Spartan 3. 5) If Adept 2 can see the Spartan 3 please load the attached bit file to verify that the Spartan 3 is working. best regards, Jon s3demo.bit
  5. Hi @Avb, If you want to add the Nexys 4 DDR board definition to Vivado HLS , you have browse to your Vivado installation folder. For example, on Windows : C:\Xilinx\Vivado 2018.3\common\config and open the VivadoHls_boards.xml file in notepad++. After this please add the following line and save it : <board name="Nexys4DDR" display_name="Nexys4-DDR" family="artix-7" part="xc7a100tcsg324c-1" device="xc7a100t" package="csg324" speedgrade="-1" vendor="digilentinc.com" /> Let us know how this works for you. This is based on this forum thread here. Best Regards, Jon
  6. Hi @rzsmi, Using the Microblaze soft core processor on a ZYNQ fpga is not trivial. The ZYNQ processor is tied to certain components as showing in the attached image below. Is there a reason you are trying to using the Microblaze processor on a ZYNQ fpga instead of the ZYNQ processor? I have not used Microblaze in a ZYNQ design as of yet. Here is a non-digilent tutorial Hello World on Microblaze UART on PS in Zynq Processor that might be helpful. thank you, Jon
  7. Hi @tauquir_iqbal, Welcome to the Digilent forums! I moved this thread to a section where more experienced AD2/WaveForms engineers look. thank you, Jon
  8. Hi @tauquir_iqbal, Welcome to the Digilent forums! I moved this thread to a section where more experienced AD2/WaveForms engineers look. cheers, Jon
  9. Hi @Wilson, I used the bit file provided in the Nexys2 Board verification Project on the Nexys 2 resource center here. I attached the ucf file for the Nexys2 Board verification Project for the 1200K. The master UCF file is also on the resource center. It sounds like the Nexys 2 1200K is working. Here is a basic Nexys 2 non-digilent tutorial that should be helpful. Are you able to go through this tutorial as expected? cheers, Jon DemoWithMemCfg.ucf
  10. Hi @Clouds42, Welcome to the Digilent Forums! cheers, Jon
  11. Hi @mehmetdemirtas89, Another option is to use the add a module function by right clicking on an empty space in the Vivado block design. The Add a module function connects VHDL/Verilog modules to the AXI bus as discussed in this and this forum thread. thank you, Jon
  12. Hi @ezadobrischi, Welcome to the Digilent Forums. Please be more specific on the Photo Diode output. Based on basic Photo Diode output I would: 1) Convert the photo diode receiver current output to voltage and use an ADC to read the voltage signal. 2) The Nexys 4 DDR has and on-board XADC (xilinx analog to digital converter) 7 Series FPGAs and Zynq-7000 SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide. Here is our XADC demo for the Nexys 4 DDR done in Verilog. 3) The voltage input range is 0v to 1v in unipolar mode and -.5v to .5v for bipolar mode for the on-board XADC. 4) If the voltage is not within the 0v -1v then I would either use a level shifter circuit to bring the analog signal into the 0-1v range or use something like the Pmod LVLSHFT. 5) If the voltage is in the 3.3v - 5v range and do not want to use use a level shifter you can use other ADC's like the Pmod AD1. Once you have the signal in the Nexys 4 DDR you can filter the signal. cheers, Jon
  13. Hi @newkid_old, Here is a verified Vivado 2018.2 Arty-A7-35T gpio interrupt project using your SDK code. Please download and run this project. Do you get the expected results. If not please attach screen shots of your serial terminal output. thank you, Jon
  14. jpeyron

    Scope in labview

    Hi @Dejvid, Welcome to the Digilent Forums! Please provide some additional details about what you are looking for. If you are wanting a VI to work with the Analog Discovery 2 here is an Instructable for using the Analog Discovery 2 with LabVIEW. thank you, Jon
  15. jpeyron

    Pmod CMPS2

    Hi @varun332, I will reach out to our content team about this issue. In the mean time I was able to verify the exiting code can be alter to work with only a few changes to the code. To fix existing code on the resource center here please use a text editor and replace the Wire.receive() with Wire.read(). Also change the #include <CMPS2.h> to #include "CMPS2.h" on the top of the CMPS2.c and the CMPS2.ino. thank you, Jon
  16. Hi @Wilson, I have attached the demo bit file for the 500K and the 1200K nexys 2 along with a screen shot and picture to help with using Adept 2 with configuring the Nexys 2 with the attached bit file. Do you have the Jumper setting the same as the attached picture? Does thye 7 segment display and leds work? cheers, Jon 500k.zip 1200k.zip
  17. Hi @Mingfei, Glad to hear you were able to get the project working. cheers, Jon
  18. Hi @hello.parth, I have PM'd you about the proprietary FTDI programming circuit. thank you, Jon
  19. Hi @jpswensen, Welcome to the Digilent Forums! I was able to get the example project on the chipKIT Motor Shield Resource Center working. I am using the Arduino IDE version 1.8.1 and the Digilent Core here. In the UC32 reference manual here on page 3 it states "17. J11 – I 2C Dedicated I2C signals. These pins are independent of the settings of jumpers JP6 and JP8. However, if JP6 and JP8 are in the RG3 and RG2 position, the I2C signals will be tied to pins A4 and A5 on J7" JP6 and JP8 need to be jumpered to RG3 and RG2. This ties the I2C signals to pins A4 and A5 on J7. These pins are used in the example demo. cheers, Jon
  20. Hi @MMateos, I just verified the above linked project works without an issue cheers, Jon
  21. Hi @Jaye, I moved this post to a section where more experienced AD2/WaveForms engineers look. thank you, Jon
  22. Hi @MMateos, Welcome to the Digilent Forums! We have the Pmod KYPD which has Verilog and VHDL examples using it with a Nexys 3 and ISE. Here is an unverified VHDL Basys 3_PmodKYPD Vivado 2018.2 project that should help with your project. cheers, Jon
  23. Hi @Wilson, Please attach the project you are using. Here is a pdf as well as the resource center here that should be helpful. thank you, Jon
  24. Hi @Wilson, 1) Is the Nexys 2 power selecting jumper set correctly? 2) Does the done led go on when the Nexys 2 is configured? 3) Please attach screen shots of what you see in adept 2. thank you, Jon
  25. Hi @Mingfei, Here is a verified HDMI-OUT with the PmodAD5 IP core added to the block design using Vivado 2018.2. I started with a fresh HDMI-out project. Then I replace the vivado library folder in the project folder here: \vivado_proj\Arty-Z7-20-hdmi-out.ipdefs\repo_0 with the vivado library from here. 1) open the project in Vivado 2018.2. 2) upgrade the IP core's by selecting reports->report IP status. 3) add the PmodAD5 IP Core 4) open the zynq processor and add a 50 MHZ clock 5) Connect the 50 MHz clock to the ext_spi_clk pin on the PmodAD5 IP Core 6) run connection automation 7) re-fresh the hierarchy and or delete and re-create the wrapper to ensure the PmodAD5 IP core is included in the wrapper. 8). update the XDC names to reflect the names in the wrapper. We upgraded some of the HDMI IP Cores and some of the Pin names are slightly different. We capitalized some of the pin names. 9) generate a bitstream, export hardware including bitstream, launch SDK. 10) create and empty application in sdk and add the PmodAD5 main.c to the scr folder of the application. 11) program fpga and right click on the application and select run as ->Launch on hardware(system debugger) thank you, Jon