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Everything posted by jpeyron

  1. jpeyron

    pmod can period

    Hi @daeroro, It looks like you have been able to alter the bit rate which was discussed in your other post here. I would suggest exposing the signals between the Pmod Can and the Zybo and using an oscilloscope on these signals. Do you have a CAN bus analyzer so you can better see what is being communicated between the Pmod CAN and the tms570 board? best regards, Jon
  2. Hi @Lightbulb, Welcome to the Digilent forums. Sorry for the late reply. For command mode the user guide on page 12 states that there is a delay that needs to be used when entering the $$$. Have you tried using a different serial terminal emulator like tera term? best regards, Jon
  3. jpeyron


    Hi @revathi, We do not have a ZC702. I did find some material for the ZC702 and the xadc her. Here and Here are some xilinx forum threads that might be helpful as well. best regards, Jon
  4. Hi @nob, I have sent you a PM about this. cheers, Jon
  5. Hi @Zorroslade000, Have you looked at the add a module function on the block design in Vivado? Here is a xilinx youtube. best regards, Jon
  6. Hi @andre19, There is a few thing that must be done to send data through the UART with a ZYNQ processor. Unfortunately we do not have the bandwidth or your development board to create a completed UART project for this board. This is my understanding of the general tasks that need to be accomplished: 1) You will need to correctly configure the ZYNQ processor. I would look at the Zynq-7000 SoC Technical Reference Manual. You can also look at our ZYNQ development board's board files and schematics as a reference. 2) You will need to constrain the output/input signals using an XDC or through a board file. best regards, Jon
  7. Hi @aliff saad, In the tool section of the Arduino IDE below the board selection you must also select the com port you would like to use. Similarly, you will also need to select the board you are using from the tools->boards section as well since it looks like the Arduino IDE thinks you are using a Basys MX3. best regards, Jon
  8. Hi @andre19, I would suggest looking at the schematic here for the pins that you will need to use in your XDC. This here might be the E310 XDC. I would suggest reaching out to ettus about resources for their board. best regards, Jon
  9. Hi @traymond160, 1) To be able to better assist you, What specific Artix-7 35T FPGA development board do you have? a) We have a few different FPGA development boards with the Axtix-7 35T on them(I.E. Cmod A7-35T, Basys 3, Arty-A7 35T). 2) Are you using Windows or linux? If you are using linux with vivado you have to manually install the digilent cable drivers as discussed here 3) We have a installing vivado tutorial here that walks you through the process of getting vivado working with our FPGA development boards. 4) We have a getting started with Vivado here that should help you with using the Artix-7 35T FPGA you have. best regards, Jon
  10. Hi @traymond160, The Artix-7 35T is an FPGA so i would suggest posting your question in the FPGA section. cheers, Jon
  11. Hi @postmaster87, Welcome to the Digilent Forums. 1) How are you powering the Zybo Z7? a) Is JP6 iset to USB? 2) Is JP5 set to JTAG? 3) Have you tried using a different USB A to Micro B cable? 4) Have you tried using a different USB port? 5) Does PGOOD LD 13 light up when the Zybo Z7 is turned on? a) If not I would like to check the power rails coming out of the power regulator. 1) with a DMM please measure the voltage on the following capacitors: Either C219, C220, C221 or C222 (should be 5 V) Either C228,or C229 (should be 3.3 V) C237 (should be 1.35 V) C240 (should be 1.8 V) best regards, Jon
  12. Hi @traymond160, Welcome to the Digilent forums! best regards, Jon
  13. Hi @shan, Welcome to the Digilent forum! Here is a xilinx forum that discusses a similar error that should be helpful for your issue. best regards, Jon
  14. Hi @andre19, We provide board files for our boards to assist with constraining some of the components like the USB UART bridge as well as the DDR. You need to use a xdc file to constrain the UART_O_0_rxd and the UART_O_0_txd signals to specific pins on your development board. Does the manufacture provide a board file or XDC for you to use? I would also suggest reaching out and or looking through your ZYNQ development board's manufacture's provided documentation/resources to see what resources they provide. best regards, Jon
  15. Hi @aliff saad, I would suggest to make sure that there are no spaces in your paths. I downloaded the library and placed it here: C:\Users\jpeyron\Documents\Arduino\libraries\SparkFun_LSM9DS1_Arduino_Library-master\examples\LSM9DS1_Basic_SPI I then opened the arduino ide using the digilent core and ran the LSM9DS1_Basic_SPI.ino with no issue as shown in the attached screen shot below. best regards, Jon
  16. Hi @Sduru, I found a xilinx forum that that discusses this issue here. For their project the .project and .cproject files were referencing an obsolete hw_platform that no longer existed. They manually edited the files to the new hw_platform--now the design worked. Did you use the 2018.2 project from the release page here? Did you import the fsbl and pcam_vdma_hdmi from the sdk_appsrc folder in the Zybo-Z7-20-Pcam-5C-2018.2.1 folder? best regards, Jon
  17. Hi @vivekraj2992, We provide board files for our FPGA development boards that include QSPI flash IP configured for the Genesys 2 as shown in the attached screen shot below. Here is a tutorial that will assist with installing the Digilent Board files. best regards, Jon
  18. jpeyron


    Hi @revathi, Please attach a picture of your XADC wiring to the ZC702 dev board along with a screen shot of the XADC wizard adc setup page. best regards, Jon
  19. Hi @Annie B, Welcome to the Digilent Forums! Glad to hear that the terminal commands worked for you. best regards, Jon
  20. jpeyron

    HID protocol on Basys3

    Hi @fpga_babe, Glad to here that your verilog module works! best regards, Jon
  21. jpeyron

    AXI4 and Vivado ILA

    Hi @Sduru, Glad to hear that the problem has been resolved! best regards, Jon
  22. Hi @andre19, Welcome to the Digilent Forums. What ZYNQ development board do you have? I would suggest following the Getting Started with Zynq tutorial along with making sure that you have the Digilent board files installed. Digilent has board files that correctly configures the ZYNQ processor along with the DDR3. Here are the tutorials that we have available Getting Started with the Vivado IP Integrator, Getting Started with Vivado, Installing Vivado and Digilent Board Files and Getting Started with Digilent Pmod IPs. I will pass on your desire for more information on the Zynq core, AXI interconnect, GPIO, proc reset IP Cores to our content team although I believe that currently we do not have the bandwidth to create tutorials for how to edit properties of the Zynq core, AXI interconnect, GPIO and the process reset IP Cores. I would suggest looking through the Zynq-7000 SoC Technical Reference Manual, AXI Interconnect v2.1 LogiCORE IP Product Guide, Processor System Reset Module v5.0 LogiCORE IP Product Guide and AXI GPIO v2.0 LogiCORE IP Product Guide. Xilinx does have a lot of documentation/examples on how to use their IP Cores available from the block design by right clicking on the IP. I would also suggest looking here (if you used the default installation path): " C:\Xilinx\SDK\2018.3\data\embeddedsw\XilinxProcessorIPLib\drivers" for examples on how to uses their IP Cores in SDK. The ZYNQ book is also a good source of information as well. If you are still having issues with the Getting Started with Zynq tutorial please attach screen shots of your block design. best regards, Jon
  23. Hi @aliff saad, Please attach a screen shot of the Arduino IDE errors. Please attach the path of where you have install the LSM9DS1 library. best regards, Jon
  24. jpeyron

    DDR3 input clock source

    Hi @mishu, I believe we added the additional oscillator to help meet timing and eliminated propagation delays with the DDR3. I have reached out to a more experienced engineer to see if they have any additional input as well. best regards, Jon
  25. Hi @PallaviCharupallli, Here is is the resource center for the Zybo Z7. The DMA Audio Demo on the resource center should help with understanding how to use the audio codec. The Digilent board files correctly configure the Zynq processor along with the DDR which is tied directly to the ARM processors. I have attached an image to help visualize the ZYNQ processor architecture. Here is the ZYNQ book that should be helpful with better understanding the DDR and Audio codec. best regards, Jon