jpeyron

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jpeyron last won the day on April 16

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About jpeyron

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  1. jpeyron

    Data compression

    Hi @Mukul, I have worked a little bit with data compression in software. I am not very experienced with using data compression in FPGA's. Hopefully one of the more experienced community members or staff will have some good input for you. best regards, Jon
  2. jpeyron

    PCIE on CMOD-A735T

    Hi @Charles Li, Welcome to the Digilent Forums! To meet a specific tier of development board not all of the FPGA's capabilities are facilitated in every Digilent FPGA development board. Here is the Cmod A7 resource center. On the schematic for the Cmod A7 you can see on page 3 what pins have been routed on banks 14, 16, 34 and 35. Here is a list of Digilent boards that have the transceivers routed. Zedboard Nexys Video Genesys 2 NetFPGA Sume best regards, Jon
  3. jpeyron

    SDK issue

    Hi @Kris Persyn, It looks like your first first screen shot with the application sw you selected empty template. You will need to add or import a main.c under the scr folder. If you expand your bsp as well as the HW platform you should be able to find the libraries included in the IP cores in your HW platform. best regards, Jon
  4. Hi @Kobi18210, Sorry for the delayed response. We do not have a project that directly transfers data through the ethernet. We have used the echo server project which should be similar process as with this tutorial here. I have attached an altered echo.c file as a potential reference. Another option would be to use an embedded linux platform like petalinux here. best regards, Jon echo.txt
  5. Hi @Sami Malik, Can you attach a screen shot of your bram IP Core setting and memory addresses for the bram. best regards, Jon
  6. jpeyron

    SOUNDS WITH VHDL

    Hi @eray, @hamster's MPU6050/Basys 3 is a good start to an interesting project. I would suggest converting audio files to a coe file using something like matlab or a prython script. Then in vivado is a bram with the coe file. Here is a xilinx forum thread that discusses this. best regards, Jon
  7. Hi @birca123, I reached out to one of my co-workers which happens to be currently having a similar issue with the Video Timing Controller on their project. We will be looking into this further but currently havent found a cause. We also would suggest to reach out to Xilinx about the Video Timing Controller hanging as well. best regards, Jon
  8. Hi @hearos, Are you using the SD card reader that is on the Nexys 4 DDR or a Pmod SD or Pmod MicroSD on pmod port JA? If you are trying to us the SD card reader on the Nexys 4 DDR then you will want to use the onboard Micro SD Slot under external memory on the board tab. I have attached a screen shot of this. If you are using a Pmod Sd or Pmod MicroSD on port JA you should not need a XDC to constrain these pins since the boards files along with the vivado library IP's configure this for you. best regards, Jon
  9. Hi @Cuikun LIN, Here is a forum thread that discusses Labview and AD2 sample code. Here is a forum thread that discusses the WaveForms Runtime/SDK which can be accessed from LabView directly without Python which is on hackster.io here. The provided examples in the SDK are mostly in Python which you might be helpful. best regards, Jon
  10. Hi @mikeWylie, Unfortunately we have not used the AD9114-DPG2-EBZ with the AD-DAC-FMC-ADP-ND adapter card. FMC's on our boards like the Nexys Video are designed to meet the 57.1 spec. The Nexys Video has a low pin count(LPC) FMC. I would also suggest contacting Analog Devices to get their input as well. best regards, Jon
  11. Hi @mufasir_qureshi, Welcome to the Digilent Forums! Could you attach all of the HDL. Can you be more descriptive about your project. best regards, Jon PS- one of my first verilog SPI controller i missed assigning the signal as an inout. Instead I had assigned it as an input.
  12. Hi @NeedlessBird, Glad to to hear that changing the Vivado version resolved the SDK driver issue. Thank you for sharing what you had to do to resolve this issue. best regards, Jon
  13. Hi @patelviv, I have moved your thread to a section where more experienced embedded linux engineers look. Here is a non digilent tutorial that might be helpful. best regards, Jon
  14. Hi @michaelgood411, Welcome to the Digilent Forums! I have moved your thread to a section where more experienced embedded linux engineers look. best regards, Jon
  15. jpeyron

    CPR 290-006

    Hi @Sergei, Welcome to the Digilent forums! I believe that the 1:19 Gear Ratio DC Motor/Gearbox has 1 pulse per revolution. Here and here are forum thread that discusses the CPR. best regards, Jon