jpeyron

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jpeyron last won the day on June 24

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About jpeyron

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  1. Hi @user2051, Please download Adept 2 here. Does Adept recognize the Zybo-Z7? I do not think I have seen this error before. Please attach a screen shot of your SDK with the hardware platform expanded. First right click on the BSP and select re-generate the board support package. If this does not work I would delete the SDK folder from your project and re-export the hardware from Vivado including the bitstream and start fresh. If you are still experience this issue I would suggest reaching out to Xilinx support here. best regards, Jon
  2. Hi @mptcultist, Please attach screen shots of your vivado block design along with your SDK with the HW_Platform expanded. best regards, Jon
  3. jpeyron

    Pmod wifi

    Hi @kavya@iiitn, Please attach a screen shot of your block design as well as the contents of the SD card you are using with the HTTPServer example. What FPGA board are you using? best regards, Jon
  4. jpeyron

    PROBLEM WITH NEXYS A7 EVB

    Hi @Alex_V, In the attached picture the Mode Jumper is set to QSPI Flash. JTAG Mode is the middle 2 pins. I would suggest using the JTAG Mode to ensure there is no issues when configuring the FPGA. Here is a screen shot of my windows device manager with a Digilent FPGA connected. I previously miss spelled the word ports as pots. You should see a com port for the FPGA as well as serial converter A and B when your Nexys A7 is connected to your PC and powered on as shown below. What about the project is not working or acting differently? What type of project are you doing? Have you tried powering the board through an external power source? Have you tried using your Nexys A7 on your friends PC? best regards, Jon
  5. Hi @newkid_old, I would suggest simulating the whole project to find where the issues are or adding the ILA module to view specific signals of interest. best regards, Jon
  6. Hi @pgmaser, Welcome to the Digilent Forums! You can use the ADD a Module function to connect a HDL module/entity to the axi bus using microblaze . Here is a forum thread that discusses this option. All of our boards use USB 2.0. The Nexys Video which has the Artix 7 fpga can be used with Gigabit Ethernet. Here is a community members gigabit project with the Nexys Video. Best regards, Jon
  7. Hi @newkid_old, I would suggest using the ILA module. Here is a Xilinx forum that discusses this. Here is the Integrated Logic Analyzer v6.2 LogiCORE IP Product Guide that should also be helpful. Best regards, Jon
  8. Hi @thk3695, I sent you a PM about this. best regards, Jon
  9. Hi @brian.dig, Glad to hear that you were able to to download the SOV. best regards, Jon
  10. Hi @AndyCap, Glad to hear you were able to get past this issue. Thank you for sharing what you did. best regards, Jon
  11. Hi @brian.dig, Welcome to the digilent forums.! I have PM'd you a copy of the SOV for the JTAG-HS3. Please let us know if you were able to download this. Best regards, Jon
  12. Hi @Y_H, The Jupyter Notebook platform along with adding additional Pmod's to this platform is supported by PINQ.IO . You will need to reach out to PYNQ.IO Support here. best regards, Jon
  13. Hi @mptcultist, Are you able to run the Getting started with Microblaze tutorial working? best regards, Jon
  14. Hi @mptcultist, What text is being sent through the USB UART COM Port and the telnet on the Serial terminal emulator? Please attach screen shots. What speed are you setting the phy_link_speed? best regards, Jon
  15. jpeyron

    PMOD CLP

    Hi @Ahmed Alfadhel, We have not had the bandwidth to create an IP Core for the Pmod CLP. We have verilog and VHDL ISE projects that can be alter to work with vivado on the Pmod CLS resource center . You will need to use the UCF file as a reference for the XDC file. You should be able to use the ADD a Module function in the Vivado Block design as discusses in this forum as well as in this xilinx YouTube to use these projects with Microblaze. You can use the add a module function as described in this Xilinx YouTube. The add a module function allow users access to the AXI bus with their VHDL Entities/Verilog Modules. Here is a forum thread that discusses this as well. best regards, Jon