jpeyron

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jpeyron last won the day on April 6

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About jpeyron

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  1. AXI Stream FIFO

    Hi @newkid_old, also how often you getting a full packet from the FIFO? thank you, Jon
  2. AXI Stream FIFO

    Hi @newkid_old, What is the clock frequency you are giving the AXI Stream FIFO? thank you, Jon
  3. AXI Stream FIFO

    Hi @newkid_old, The AXI Stream FIFO looks to be the best Memory device for your situation. Also to clarify what frequency are you planning on moving data from the ADC? thank you, Jon
  4. AXI Stream FIFO

    Hi @newkid_old, Could you clarify what you mean by storage device and what your project is? thank you, Jon
  5. HDMI In to VGA out on Zybo

    Hi @cgarry, We currently do not have a basic project with these ip cores that does not have a processor involved. I have reached out to more experience engineers about your thread to see if they have any other input. Could you please attach your time errors? thank you, Jon
  6. SPI_SLAVE_intr_example not working

    Hi @rahulgujaran, I would suggest to scope the external pins along with using the SDK debugger to better see what is going on. thank you, Jon
  7. How To Program The Quad-spi Flash On The Basys3.

    Hi @Ankit, We responded to your question on your other thread here. thank you, Jon
  8. zybo: lading bit file to SPI flash using Vivado

    Hi @Ankit, You can also erase the flash with the hardware manager in Vivado. You could make your own custom application to do this with Adept 2 sdk thank you, Jon
  9. Zybo HDMI untouched design not meeting timing req.

    Hi @Casio342, For confirmation of getting the project working, it may be good to test out the project in Vivado 2016.4 since that is what it was designed in. thank you, Jon
  10. How to make led wall with FPGA?

    Hi @Riteshkakkar, I have not made a led wall for video purposes. Here is a link to FPGA4FUN dealing with led displays. Here is a led display we made for the snake game. thank you, Jon
  11. Transform pins into Pmods

    Hi @tester11, You can use pin IO0-13 and A0-A11 as shown in the reference manual in section 16. All of the pins on the pmod ports are connected in the Arty-Z7-10.I do not see an issue with your third GPIO. thank you, Jon
  12. Arty Artix-35T complete xdc

    Hi @Trillian, The master xdc is here. The pins that are not in the xdc are accessible in the schematic here. The power and ground pins on J7 would not be accessible pins connected to the fpga. You are correct with the vp and vn pins being k9 and j10. thank you, Jon
  13. Transform pins into Pmods

    Hi @tester11, Do you have the Arty-Z7-10 or Arty-Z7-20?. The shield connector has 49 pins connected to the Zynq PL for general purpose Digital I/O on the Arty Z7-20 and 26 on the Arty Z7-10 as discussed in the reference manual here. thank you, Jon
  14. AXI Stream FIFO

    Hi @newkid_old, I have not work with the axi-stream fifo. I would suggest to look at the AXI4-Stream FIFO v4.1 LogiCORE IP Product Guide. Might need to put in a delay after writing to read data. thank you, Jon
  15. uartlite interrupt not working

    Hi @nattib, Here is an older tutorial that walks through setting up the uart with interrupts for the nexys video. Unfortunately it then only uses the hello world template in sdk. Here is a xilinx forum thread that has a gpio interrupt example. I am not seeing anything wrong with your sdk code. I have not used the uart/gpio interrupts in this way. Also i believe the uart tx and rx are labelled from the pc's point of view and not the FPGA's. thank you, Jon