jpeyron

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jpeyron last won the day on January 11

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About jpeyron

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  1. XADC conversion rate

    Hi @cristian_zanetti, I am not seeing anything specifically about your configuration that would cause this. Have you tried changing your averaging configuration? I would alter the xadc configurations until i found the setting that is affecting the performance. I would also look at this demo as a basic reference for setup. thank you, Jon
  2. Can I use a JTAG-SMT2-NC to program an I2C EEPROM ?

    Hi @Robert Pearce, I reached out to our design engineer about your thread and they responded with "I2C is an open collector protocol. The SMT2 uses push-pull drivers, and not open drain buffers on TMS, TDI, and TCK. Each of those buffers are tri-state buffers and they do have individual enable pins hooked up to the FTDI chip so it may be possible to do this by tieing TDI and TDO together. However, it’s going to require a lot of manual shift operations operations to implement it because of the ACK bit. Additionally, they are going to have to be real careful to ensure that the enable pins of the buffers are driven to the correct state at the correct time. They will also need external pull-ups, as 100K isn’t going to cut it. There is no Adept SDK API that will let you drive the SMT2 pins in the manner required for I2C so this will have to be done using D2XX API’s directly. I think it would be a lot easier to use an SPI ROM since the SMT2 supports that protocol." thank you, Jon
  3. Hi @Bryce, At the bottom of the Arty resource center here is the 3D CAD model. thank you, Jon
  4. How to connect DMA with microblaze ?

    Hi @Thausikan, We also have this demo for the Genesys 2 which has Kintex-7 here. thank you, Jon
  5. arty xc7S50 vivado support win 8.1

    Hi @DigitalConfig, At this point I would try reaching out to Xilinx to see if they have any suggestions for the error message saying api-ms-crt-runtime-|1-1-0.dll Is missing. I did not see anything in their forum about window 8.1 and the newer versions of Vivado. Here the xilinx support suggests to re-install program when the program cannot start because api-ms-win-crt-runtime-l1-1-0.dll is missing from your computer. I also found a youtube video that might be helpful here. thank you, Jon
  6. arty xc7S50 vivado support win 8.1

    Hi @DigitalConfig, The bug was in the Vivado Webpack Edition with using the MIG in Vivado 2017.1-2017.3 for the Arty-S7-50. We worked with xilinx and got the issue resolved in Vivado 2017.4 Webpack Edition. Here is the forum thread for the issues with the MIG. There was no issue in the with the MIG for the Arty-S7-50 in Vivado design editions 2017.1-2017.3. We do not control what the xilinx page says and it has likely been updated to reflect the newest features of 2017.4. For the 2016.4 release notes from Xilinx that version of Vivado does support Windows 8.1, but it does not support Spartan-7 devices. I would suggest to install Vivado 2017.4 on you Windows 8.1 machine to see if you experience issues. thank you, Jon
  7. Hi @Tifei, You should install all 3, system, utilities and SDK. You can install them in either window 7 professional or Window 10 pc. In the Adept 2 SDK folder that is downloaded there are examples for both the DMRG and DJTG libraries. cheers, Jon
  8. arty xc7S50 vivado support win 8.1

    Hi @DigitalConfig, The Arty-S7-50 is a new board using a new Xilinx FPGA. The Arty-S7-50 was only added last year in Vivado 2017.1 and on going. If you are planning on using the Webpack version I would suggest to use the Design edition. The webpack edition had issues with the MIG on the Arty-S7-50 up until the newest version Vivado 2017.4. You can use the design edition at no cost as long as you not targeting at design edition required FPGA. The Arty-S7-50 does not require you to have the design edition. Unfortunately xilinx does not support window 8.1 on any of the versions of Vivado that would be able to use the Arty-S7-50 shown here. I does look like you should be able to use Vivado 2017.4 on a window 8.1 OS but might experience some issue and crashed as shown here. I do know that window 10 is supported if you were able/willing to upgrade your window 8.1 machine. thank you, Jon
  9. What Xilinx SDx project type for Arty Z7

    Hi @hbrednek, I have not used the SDx software. We do not have any resources for the SDx software. Unfortunately, we have not had the opportunity to create these materials. thank you, Jon
  10. Nexys Video HDMI Demo boot from QSPI Flash

    Hi @Ben_Cook, In the Vivado block design for the Nexys video hdmi you would need to add the QSPIFLASH and the system clock from the board tab to the design. Then in the clock wizard add an output clock of 50 MHz and connect that to the ext_spi_clk on the QSPIFLASH IP core.Then click on connection automation and validate the design. Next I typically delete the wrapper and re-create the wrapper so it insures that the wrapper includes the new additions. I then generate a bitstream. Then you will be able to use the srec spi bootloader in sdk. cheers, Jon
  11. Nexys Video HDMI demo problem

    Hi @john2018, The Nexys Video HDMI project was made to work with VIvado 2016.4. The vivado version makes a difference. To use this project in Vivado 2017.4. You should first double click on cleanup in the project folder of the project. Next make sure that there is contents in the repo->vivado library folder. Then use the tcl script to load the project into vivado 2017.4. Next click on tools->reports->report ip status and click to upgrade and upgrade/generate the IP cores. Next change the ddc_sda_io to DDC_sda_io and ddc_scl_io to DDC_scl_io in the xdc. This is done because the pin names changed when we updated the DVI2RGB IP core. Then create a wrapper and generate a bitstream. thank you, Jon
  12. Hi @Tifei, For question number one, we recommended the JTAG-HS2 since it is a newer programming cable and has more support. For question number two, the AVR programmer still has a place in this world but only for very specific older AVR chips. Lastly for question number 3, you would be using Adept SDK. In this case you would use the DMGR and DJTG libraries to write your own custom application. cheers, Jon
  13. Hi @Tifei, I reached out to our design engineer about this thread and they responded suggesting the JTAG-HS2 instead of the JTAG USB. The VREF pin on the module uses the VDD voltage level supplied by the host board and will work with voltages between 1.8V and 5.0V. Adept can program some FPGAs but isn’t a general FPGA programmer, which is why he would point customers to the Xilinx Vivado tools for that. The AVR programmer hasn’t been updated in years so you would have to get really lucky in selecting a part that’s actually supported. Unfortunately, a reference manual for the JTAG USB was not made . The Reference manual for the JTAG HS2 is here. thank you, Jon
  14. simple wishbone demo to read switches write leds

    Hi @toastedcpu, I have not worked with the wishbone bus. Here and here are some threads that discuss the wishbone bus. thank you, Jon
  15. Arty S7-50 High Speed PMOD impedance

    Hi @hawdai, In the reference manual here in section 8.2 High-Speed Pmod it show that traces are routed 100 ohm (+/- 10%) differential. Cheers, Jon