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jpeyron last won the day on August 13

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  1. Hi @JessPlazas, Its in the same spot. I have attached a screen shot below. cheers, Jon
  2. Hi @JessPlazas, In Vivado, you left click on language templates, choose the language(i choose Verilog), select Device Primitive Instantiation, select Artix-7, select Advanced and lastly select Xilinx Analog-to-Digital Converter(XADC). Here is a Xilinx forum thread that might be helpful. Here is the 7 Series FPGAs and Zynq-7000 All Programmable SoC XADC Dual 12-Bit 1 MSPS Analog-to-Digital Converter User Guide as well. cheers, Jon
  3. Hi @renanj, Looking at the BOM, both the 10k and 20K resistors are 1%. cheers, Jon
  4. Hi @JessPlazas, Here is our github xadc project for the Nexys 4DDR. Here is the coresponding tutorial. This is done in Vivado 2016.4. Once you have opened it you can double click on the xadc wizard and adjust the adc conversion rate along with many other parameters. cheers, Jon
  5. Hi @Mark1000, The Spartan 3E starter kit board includes an on-board USB-based JTAG programming interface. The on-chip circuitry simplifies the device programming experience. In typical applications, the JTAG programming hardware resides off-board or in a separate programming module, such as the Xilinx Platform USB cable, JTAG-HS2 or JTAG-HS3 which on the Spartan 3E starter is I believe connected on J28. Here is the resource page which has the reference manual , schematic, User guide as well as some reference designs. cheers, Jon
  6. Hi @Mark1000, Unfortunately, ISE is need for making the bit file. Once you have made the bit file you can load the bit file on the Spartan-3E using iMPACT(part of ISE) or our Adept 2 software through USB. ISE is not supported on window 8.1 or 10 although Here is a Xilinx forum thread that deals with ways to get ISE working in windows 8.1 and 10. thank you, Jon
  7. Hi @jpiat, I just completed the tutorial. You should select add memory configuration device instead of Boot from memory device as shown in section 4 of the tutorial you linked. cheers, Jon
  8. Hi @FarmerJo, I got the VHDL code to work. I attached both files for the custom IP. Also in the sdk code change the for loop to: for(i=0;i<35000; i++); for more visible results. So in the comparator statements that drive the PWM signal you need to compare similar types so I converted counter from and integer to a std_logic_vector. I have also attached my completed project in Vivado 2017.2. cheers, Jon myip_v1_0.vhd myip_v1_0_S00_AXI.vhd
  9. Hi @desmond, I have sent you a private message about your question. cheers, JOn
  10. Hi @omn0mn0m, The ZYNQ can sustain up to +85 Celsius degrees operational temperature. I do not think the heat you mentioned with having the board connected a web browser is a problem. In the other thread the customer had the pynq image for booting and with jupyter note book the on board temperature sensor graph was around 67 degree Celsius only after just booting and powered though USB.. Since you have already added a heat sink you can also use a fan for the PYNQ-Z1. Unfortunately, we do not sell fans but hopefully you can find a small fan locally, if you fear that the temperature will deteriorate your device. thank you, Jon
  11. Hi @rdk9000, After looking at the voltage constant on the data sheet here. r/min is Revolutions per minute or rpm. The mV/r/min relationship is voltage over speed. cheers, Jon
  12. Hi @cjcamara, Glad to hear it is working! Thank you for sharing what happened. cheers, Jon
  13. Hi @gutielo, I reached out to one of our design engineers. What i found out is that the pin is an output and intend to power a peripheral board. The XADC itself is powered via the VCCADC on the Zynq, which is powered by an onboard regulator. We followed Xilinx’s spec for the header so it’s more or less the same as the XADC header on any of Xilinx’s series 7 evaluation boards. The design engineer believes the purpose of this particular pinout was to make it compatible with the following board: Sorry about the delay. cheers, Jon
  14. Hi @fank, After talking with a co-worker more about your questions we decided that the best course of action would be to not use the add_a_block feature but instead use the PmodSF3 IP core(validated) that is here and change it to work for the PmodSF. You will want to look at the datasheet for the IC on the PmodSF3 here and compare it with the datasheet for the IC on the PmodSF here. Main change is that only single pin spi is available, so you can ignore all of the write dual and quad stuff. The 5 important commands have the same codes. So virtually no change necessary, other than cutting interrupt requirement and removing the quad/dual read/write tests. Sorry for the inconvenience. cheers, Jon
  15. Hi @D@n, You are not missing anything. We have not released a WaveForms 2016 or WaveForms 2017 since we have not come out a with major release since WaveForms 2015. WaveForms 2015 is our current software for the Analog Discovery 1 & 2, Electronic Explore board and the Digital Discovery which is here. The last update to WaveForms 2015 was 3.6.8 - August 8th, 2017. Here is a link to the change log for WaveForms 2015. If you were to download WaveForms here it would take you to a page where you can download WaveForms 2 (legacy) which we are not actively updating. cheers, Jon