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  1. Hi, I'm using XSDB shell to initialize my soc on zedboard. When I hit the command "xsdb% ps7_init" i get the error "AP transaction error, DAP status f0000021". Is there someone who met this error and can provide me a hint?
  2. @artvvb Thank you Arthur. You helped me a lot with your responses. Now i try to figure out how to use a parallelized mechanism. I created two blocks that function as two comparators. There are 2 different address created for that blocks(0x43C10000 and 0x43c20000 - each has 64k). In sdk, I need to write secvential in that two addresses, resulting a non parallelized mannerr. How can I achive a parallelized manner send data to that two comparators?
  3. @Notarobot @artvvb Sorry about this. I just wanted to know how the output of test IP is manipulated inside. I made a simple assign to the ouput wire "result"(see pic3-ip.png) but always give me in the user program value 0 instead value 8 (see pic2-sdk.png ). What i have to change to give the right value (8) in user program ? Sorry for this wrong situation.
  4. @artvvb Thank you for your time and also for your picture. Can you please upload the test IP, or the entire project to use it as an exemple? First i want to calculate the sum of two numbers in PL and print it out in user program. I can not find a trivial tutorial to make this trivial thing entirly. I saw in this tutorial that data sent from PS to PL is written to a specific address generated for my IP, which can be seen in "Vivado - Address Editor". Writing in user program with Xil_Out32() function to this address produce the filling up of registers slv_reg# inside the IP. I tried to put my data that i want back in PS into slv_reg3 for exemple, and then to access that value from user program throught Xil_In32() function but I get the following error ("slv_reg3 has multiple drivers"). I saw that for comunication PL-PS from user program, i need to user Xil_Out32() and Xil_In32(). Thank you, Mihai
  5. @artvvb I'm trying to figure out how to get back to PS the data processed in FPGA. In the tutorial that you pointed to me, data received in FPGA ends up there by pulsing the leds. I want to get back that data and print out in user program.
  6. @artvvb Thank you for your very quick answer. For now, I want that these 4 registers to be initialized at FPGA initialization. After this stage, I want to use a FIFO mechanism because these FPGA register will store temporally data. Finally i want to know if a string (picture - B entry from the comparator) is within a vector of strings (picture - A entry).
  7. Hi, I want to implement in Vivado a hardware implementation which will program the FPGA to create 4 register of 128 bit data and 4 comparators. First entries of the comparators will be linked to these 4 registers and the other entries will be linked to a single 128 bit register received from PS. I attached i picture (A picture is worth a thousand words). Please guide me with an exemple, start point in solving this issue.
  8. Thank you for your answers. @D@n I really want to involve PL part in this project because my project must be a proof of concept for acceleration of string matching in hardware. @Notarobot I want to develop an educational project for a full 1 month term. Being a school project, the signature database(string database) will be a not very big one, just to prove that the hardware implementation is faster in term of time than software implementation.
  9. An answer will be very usefull for me to know in which direction to take. I want to make an IDS on Zedboard. I want to get the payload from each TCP/IP packet received throught eth interface and sent it to PL from PS part. In the PL part i also need a data base of payloads' s signature already known as malicious for comparing each payload received from PS part. First of all i dont know if this a good ideea and then I don't know how to manage the data base of signatures in PL part(maybe through a new stream connected directly through eth interface to an external data base, since the date base will be quite large in size). Do you think it is suitable for me to make my project in the way described above?
  10. Hello everyone, I kindly ask for some start points that may help me in developing an linux application, on zedboard that inspect the payload of tcp/udp package received through eth interface. I had search a lot on internet/forums about this subject but i could not find some strong hints.
  11. fpga

    Hi Jon, Did you reached out to the engineer that will be able to give me a response about 'xililinux vs petalinux' ?
  12. fpga

    Hi Jon, Thank you for your quick answer. I configure my zedboard to run Xillinux distribuition (xillinux). I saw that this distribuition has already drivers for AXI4 bus (xillybus). I need to mention that this will be a school project. Should i use Petalinux instead ?
  13. fpga

    Hi everyone, I want to implement an intrustion detection system on zedboard. I want to use PL for string matching and PS to handle the interrupts on possitive detection. Being a beginner in this area(FPGA + networking) I would like to know if this is possible and any informations or any type of instructions or steps that can help me is tremendously appreciated.