Maciej Piechotka

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Everything posted by Maciej Piechotka

  1. Sorry - it looks like I misread the code. HDMI HPD needs to be set out output and set to 1 when active.
  2. @jpeyron Setting aside that hdmi-in sample doesn't really use HDMI HPD it fails to generate bitstream: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (4) is greater than number of available sites (0). The following are banks with available pins: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: BiDi RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 4 sites. Term: DDC_scl_io Term: DDC_sda_io Term: IIC_0_scl_io Term: and IIC_0_sda_io [Place 30-374] IO placer failed to find a solution Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | IO Placement : Bank Stats | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | 0 | 0 | 0 | | | | | | | | 13 | 0 | 0 | | | | | | | | 34 | 50 | 11 | LVCMOS33(11) | | | +3.30 | YES | | | 35 | 50 | 29 | LVCMOS33(21) TMDS_33(8) | | | +3.30 | YES | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | | 100 | 40 | | | | | | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ IO Placement: +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | BankId | Terminal | Standard | Site | Pin | Attributes | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 34 | btns_4bits_tri_i[0] | LVCMOS33 | IOB_X0Y9 | R18 | | | | btns_4bits_tri_i[1] | LVCMOS33 | IOB_X0Y1 | P16 | | | | btns_4bits_tri_i[2] | LVCMOS33 | IOB_X0Y14 | V16 | | | | btns_4bits_tri_i[3] | LVCMOS33 | IOB_X0Y36 | Y16 | | | | sws_4bits_tri_i[1] | LVCMOS33 | IOB_X0Y2 | P15 | | | | sws_4bits_tri_i[2] | LVCMOS33 | IOB_X0Y41 | W13 | | | | sws_4bits_tri_i[3] | LVCMOS33 | IOB_X0Y32 | T16 | | | | vga_b[0] | LVCMOS33 | IOB_X0Y21 | P20 | | | | vga_g[1] | LVCMOS33 | IOB_X0Y22 | N20 | | | | vga_hs | LVCMOS33 | IOB_X0Y23 | P19 | | | | vga_vs | LVCMOS33 | IOB_X0Y49 | R19 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 35 | TMDS_clk_p | TMDS_33 | IOB_X0Y74 | H16 | | | | TMDS_clk_n | TMDS_33 | IOB_X0Y73 | H17 | | | | TMDS_data_p[0] | TMDS_33 | IOB_X0Y92 | D19 | | | | TMDS_data_n[0] | TMDS_33 | IOB_X0Y91 | D20 | | | | TMDS_data_p[1] | TMDS_33 | IOB_X0Y98 | C20 | | | | TMDS_data_n[1] | TMDS_33 | IOB_X0Y97 | B20 | | | | TMDS_data_p[2] | TMDS_33 | IOB_X0Y96 | B19 | | | | TMDS_data_n[2] | TMDS_33 | IOB_X0Y95 | A20 | | | | HDMI_OEN[0] | LVCMOS33 | IOB_X0Y87 | F17 | * | | | hdmi_hpd_tri_o[0] | LVCMOS33 | IOB_X0Y90 | E18 | | | | leds_4bits_tri_io[0] | LVCMOS33 | IOB_X0Y54 | M14 | | | | leds_4bits_tri_io[1] | LVCMOS33 | IOB_X0Y53 | M15 | | | | leds_4bits_tri_io[2] | LVCMOS33 | IOB_X0Y99 | G14 | | | | leds_4bits_tri_io[3] | LVCMOS33 | IOB_X0Y93 | D18 | | | | sws_4bits_tri_i[0] | LVCMOS33 | IOB_X0Y61 | G15 | * | | | vga_b[1] | LVCMOS33 | IOB_X0Y85 | M20 | | | | vga_b[2] | LVCMOS33 | IOB_X0Y80 | K19 | | | | vga_b[3] | LVCMOS33 | IOB_X0Y72 | J18 | | | | vga_b[4] | LVCMOS33 | IOB_X0Y64 | G19 | | | | vga_g[0] | LVCMOS33 | IOB_X0Y71 | H18 | | | | vga_g[2] | LVCMOS33 | IOB_X0Y82 | L19 | | | | vga_g[3] | LVCMOS33 | IOB_X0Y79 | J19 | | | | vga_g[4] | LVCMOS33 | IOB_X0Y65 | H20 | | | | vga_g[5] | LVCMOS33 | IOB_X0Y69 | F20 | | | | vga_r[0] | LVCMOS33 | IOB_X0Y86 | M19 | | | | vga_r[1] | LVCMOS33 | IOB_X0Y81 | L20 | | | | vga_r[2] | LVCMOS33 | IOB_X0Y66 | J20 | | | | vga_r[3] | LVCMOS33 | IOB_X0Y63 | G20 | | | | vga_r[4] | LVCMOS33 | IOB_X0Y70 | F19 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. [Common 17-69] Command failed: Placer could not place all instances
  3. I tried to use HDMI input but I cannot get it to work. I initialize the GPIO for HDMI HPD and HDMI OUT EN. Set the latter to 0. However HDMI HPD is 0 all the time - even if I plug the cable. The host doesn't seem to recognize connection either. Am I missing something? test.pdf
  4. @jpeyron Thanks. That one seems to work for simple designs but for more complicated designs it seems to place clocks in incorrect positions but I start separate thread for it.
  5. @jpeyron I've attached tcl and wrapper. Please let me know if you need something else. test.tcl test_wrapper.v
  6. @jpeyron Any progress? It doesn't seem to work even with attached constraints: [DRC UCIO-1] Unconstrained Logical Port: 8 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: hdmi_in_data_p[2:0], hdmi_in_data_n[2:0], hdmi_in_clk_n, and hdmi_in_clk_p.
  7. Ok. Problem was the emulated USB controller. I needed to switch to Q35/nec-xhci. I managed to get it working.
  8. @jpeyron Yes - I have installed board files. I've checked that the project is set to Zybo board. On Xilinx forum they think this is problem with drivers.
  9. Hmm. I can program FPGA but if I try to run using system debugger it immediately disconnects: :37:10 INFO : Jtag cable 'Digilent Zybo 210279A42857A' is selected. 19:37:10 INFO : 'jtag frequency' command is executed. 19:37:10 INFO : Sourcing of '/home/mpiechotka/test/test.sdk/test_wrapper_hw_platform_0/ps7_init.tcl' is done. 19:37:10 INFO : Context for 'APU' is selected. 19:37:10 INFO : Hardware design information is loaded from '/home/mpiechotka/test/test.sdk/test_wrapper_hw_platform_0/system.hdf'. 19:37:10 INFO : 'configparams force-mem-access 1' command is executed. 19:37:10 INFO : Context for 'APU' is selected. 19:37:10 INFO : 'stop' command is executed. 19:37:28 INFO : 'ps7_init' command is executed. 19:37:28 INFO : 'ps7_post_config' command is executed. 19:37:28 INFO : Context for processor 'ps7_cortexa9_0' is selected. 19:37:28 INFO : Processor reset is completed for 'ps7_cortexa9_0'. 19:37:29 INFO : Context for processor 'ps7_cortexa9_0' is selected. 19:37:29 ERROR : Memory write error at 0x100000. Invalid DAP ACK value: 0 19:37:29 INFO : ----------------XSDB Script---------------- connect -url tcp:127.0.0.1:3121 source /home/mpiechotka/test/test.sdk/test_wrapper_hw_platform_0/ps7_init.tcl targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent Zybo 210279A42857A"} -index 0 loadhw -hw /home/mpiechotka/test/test.sdk/test_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] configparams force-mem-access 1 targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent Zybo 210279A42857A"} -index 0 stop ps7_init ps7_post_config targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent Zybo 210279A42857A"} -index 0 rst -processor targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent Zybo 210279A42857A"} -index 0 dow /home/mpiechotka/test/test.sdk/test/Debug/test.elf ----------------End of Script---------------- If I try to use gdb instead it fails in ps7_init: 19:40:18 WARN : Given XMD transaction timeout value is invalid. Using default value of 60000 milli seconds 19:40:18 WARN : Given XMD transaction timeout value is invalid. Using default value of 60000 milli seconds 19:40:18 WARN : Given XMD transaction timeout value is invalid. Using default value of 60000 milli seconds 19:40:18 ERROR : Unexpected error while launching program. com.xilinx.sdk.targetmanager.TMException: Cannot flush JTAG buffers at com.xilinx.sdk.targetmanager.internal.TM.connectToProcessor(TM.java:478) at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.runTargetSetup(XilinxAppLaunchConfigurationDelegate.java:503) at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.runApplication(XilinxAppLaunchConfigurationDelegate.java:616) at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.launch(XilinxAppLaunchConfigurationDelegate.java:309) at com.xilinx.sdk.debug.ui.XilinxAppLaunchDelegateWrapper.launch(XilinxAppLaunchDelegateWrapper.java:31) at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:885) at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:739)
  10. Ok. I needed to connect to server via HW manager and decrease the JTAG frequency. For whatever reason the auto-selected one was too high.
  11. @jpeyron It seems to be something more complicated. I tried to open it in HW manager and I got following error: open_hw_target INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210279A42857A ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210279A42857A. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-register this hardware target. open_hw_target: Time (s): cpu = 00:00:03 ; elapsed = 00:00:17 . Memory (MB): peak = 6274.699 ; gain = 0.000 ; free physical = 13077 ; free virtual = 14425 ERROR: [Common 17-39] 'open_hw_target' failed due to earlier errors. ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210279A42857A The code in target seems to match the serial number of board: Found 1 device(s) Device: Zybo Product Name: Digilent Zybo User Name: Zybo Serial Number: 210279A42857 I reinstall the whole OS but w/out success.
  12. @jpeyron Yes (well - via sudo but that shouldn't matter).
  13. @jpeyron No. Last time when I installed as root Vivado HLS did not work. With regard to system -i t is almost pure CentOS (I don't think I installed anything outside tools) installation in VM. I installed the digilent utils/libraries from rpm. I tried to run install script from vivado (as root). I'm not sure what else might be relevant.
  14. @JColvin The problem with section 3 and 6 is that they refer to TMDS Clk only. However the problem seems to be in RefClock which is only documented as 200 MHz in section 4 and 5 - signal is literally described as "200 MHz reference clock" in signal description... It might be that someone more familiar with FPGAs and/or DVI might've deduce it from documentation but after reading 3 times after I know what the solution is I have no idea how was I suppose to get it from documentation
  15. Thanks. I just figure it out yesterday (I thought that I posted update). However where is the guide? The one I was using refers to clock consistently as 200 MHz. There is mention about problems but it seems to be connected from the guide to be for HDMI clock recovery. It might be clear for someone that already knows that but if one tries to figure it out it's rather opaque.
  16. It's probably n-th thread about it but I cannot manage to get the Vivado to recognize cable. $ djtgcfg init -d Zybo Initializing scan chain... Found Device ID: 13722093 Found Device ID: 4ba00477 Found 2 device(s): Device 0: ARM_DAP Device 1: XC7Z010 However when I go to Vivado it shows no devices connected to local. I have tried various things from google but none seemed to work (such as installing cable drivers by script from /opt/Vivado/... etc.).
  17. [DRC PDRC-34] MMCM_adv_ClkFrequency_div_no_dclk: The computed value 1650.165 MHz (CLKIN1_PERIOD, net CLK_IN_hdmi_clk) for the VCO operating frequency of the MMCME2_ADV site MMCME2_ADV_X0Y0 (cell test_i/dvi2rgb_0/U0/TMDS_ClockingX/DVI_ClkGenerator) falls outside the operating range of the MMCM VCO frequency for this device (600.000 - 1200.000 MHz). The computed value is (CLKFBOUT_MULT_F * 1000 / (CLKINx_PERIOD * DIVCLK_DIVIDE)). Please run update_timing to update the MMCM settings. If that does not work, adjust either the input period CLKINx_PERIOD (6.059999), multiplication factor CLKFBOUT_MULT_F (10.000000) or the division factor DIVCLK_DIVIDE (1), in order to achieve a VCO frequency within the rated operating range for this device. I tried to use both clocking wizard and clock from Zynq. I set them to 200 MHz but I got the error above. What have I done wrong?
  18. My own project. Strangely it happens when I drag'n'drop 'HDMI In' connector from the 'Board' panel. If I create manually connector named 'DDC' the warning is gone.
  19. I'm trying to use HDMI port on my Zybo board. On Vivaldo 2017.2 I run into problems when generating bitstream: [DRC NSTD-1] Unspecified I/O Standard: 3 out of 141 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: hdmi_in_ddc_scl_io, hdmi_in_ddc_sda_io, and hdmi_in_hpd_led_tri_io[0]. [DRC UCIO-1] Unconstrained Logical Port: 11 out of 141 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: hdmi_in_ddc_scl_io, hdmi_in_ddc_sda_io, hdmi_in_data_p[2:0], hdmi_in_data_n[2:0], hdmi_in_clk_n, hdmi_in_clk_p, and hdmi_in_hpd_led_tri_io[0]. How should I specify correct constraints? What have I done wrong (i.e. why they aren't specified automatically)?
  20. @jpeyron I know those documents. However after reading them many times I find them both too detailed and underspecified. For example: I assume the format is RGB not RBG (as documented) on output. Otherwise both IP and interface are misnamed. It still don't answer if the VSYNC is kept high through the whole period or is it a pulse? With regard to VDMA what format is it stored in? I assume it is just a bitmap but are RGB aligned to 1 byte (3 byte addressing) or 4 bytes [After a though - AXI is power of 2 so it must be 32-bit aligned]? What happens if the data is shorter then VSIZE or HSIZE [EDIT: It seems that it sends VDMAIntErr]? I assume it goes to next stride (EDIT: no it does not] but is it possible to recover original resolution or do I need to count manually? What is memory coherence when using SoC HS Axi by VDMA. I assume, though I haven't found it documented anywhere, that HS AXI will reply on BRESP after it hits data accessible by other ports and CPU (assuming that non-cached access is used). In other words if there is write W1 and read R1 the R1 happens-after W1 (in memory model sense) iff BRESP for W1 has been issued. But does the VDMA waits synchronously on it before proceeding to next frame [i.e. is there a system membar between frames]?
  21. Thanks @jpeyron. I know about those examples but, well, examples are not reference documentation. I didn't know about Video In to AXI Stream component but even building atop the example I would need to know how to program the VDMA and since I want to access frames in different way then write them it doesn't fully help.
  22. @[email protected] Thanks. I know what the signal are and why they were needed. For now I hoped to avoid and use ready components such as Digilent dvi2rgb. With regard to AXI - sorry I haven't clarified. I was hoping to use SystemC Xilinx abstraction and library which has AXI4M_bus_port - but no real description of how it behaves. I have read the spec. Similarly I need to use it in a sense as on Zybo board memory is exposed as 4+1 AXI Slave interfaces.
  23. Hi, I'm new to FPGAs and I have trouble finding documentation. In particular: How exactly VSync and HSync is handled for HDMI input? What can I assume about them? I'd like to create a AXI Master to store input in DDR. However I cannot find a reference for AXI4M_bus_port - how is timing handled for write_burst? Are there any guaranteed on ordering of stores through AXI Master to DDR? Matt