Maciej Piechotka

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  1. Sorry - it looks like I misread the code. HDMI HPD needs to be set out output and set to 1 when active.
  2. @jpeyron Setting aside that hdmi-in sample doesn't really use HDMI HPD it fails to generate bitstream: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (4) is greater than number of available sites (0). The following are banks with available pins: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: BiDi RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 4 sites. Term: DDC_scl_io Term: DDC_sda_io Term: IIC_0_scl_io Term: and IIC_0_sda_io [Place 30-374] IO placer failed to find a solution Below is the partial placement th
  3. I tried to use HDMI input but I cannot get it to work. I initialize the GPIO for HDMI HPD and HDMI OUT EN. Set the latter to 0. However HDMI HPD is 0 all the time - even if I plug the cable. The host doesn't seem to recognize connection either. Am I missing something? test.pdf
  4. @jpeyron Thanks. That one seems to work for simple designs but for more complicated designs it seems to place clocks in incorrect positions but I start separate thread for it.
  5. @jpeyron I've attached tcl and wrapper. Please let me know if you need something else. test.tcl test_wrapper.v
  6. @jpeyron Any progress? It doesn't seem to work even with attached constraints: [DRC UCIO-1] Unconstrained Logical Port: 8 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint def
  7. Ok. Problem was the emulated USB controller. I needed to switch to Q35/nec-xhci. I managed to get it working.
  8. @jpeyron Yes - I have installed board files. I've checked that the project is set to Zybo board. On Xilinx forum they think this is problem with drivers.
  9. Hmm. I can program FPGA but if I try to run using system debugger it immediately disconnects: :37:10 INFO : Jtag cable 'Digilent Zybo 210279A42857A' is selected. 19:37:10 INFO : 'jtag frequency' command is executed. 19:37:10 INFO : Sourcing of '/home/mpiechotka/test/test.sdk/test_wrapper_hw_platform_0/ps7_init.tcl' is done. 19:37:10 INFO : Context for 'APU' is selected. 19:37:10 INFO : Hardware design information is loaded from '/home/mpiechotka/test/test.sdk/test_wrapper_hw_platform_0/system.hdf'. 19:37:10 INFO : 'configparams force-mem-access 1' command is executed. 19:37:10 INFO : Conte
  10. Ok. I needed to connect to server via HW manager and decrease the JTAG frequency. For whatever reason the auto-selected one was too high.
  11. @jpeyron It seems to be something more complicated. I tried to open it in HW manager and I got following error: open_hw_target INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210279A42857A ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210279A42857A. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-register this hardware target. open_hw_target: Time (s): cpu = 00:00:03 ; elapsed = 00:00:17 . Memory (MB): peak = 6274.699 ; gain = 0.
  12. @jpeyron Yes (well - via sudo but that shouldn't matter).
  13. @jpeyron No. Last time when I installed as root Vivado HLS did not work. With regard to system -i t is almost pure CentOS (I don't think I installed anything outside tools) installation in VM. I installed the digilent utils/libraries from rpm. I tried to run install script from vivado (as root). I'm not sure what else might be relevant.
  14. @JColvin The problem with section 3 and 6 is that they refer to TMDS Clk only. However the problem seems to be in RefClock which is only documented as 200 MHz in section 4 and 5 - signal is literally described as "200 MHz reference clock" in signal description... It might be that someone more familiar with FPGAs and/or DVI might've deduce it from documentation but after reading 3 times after I know what the solution is I have no idea how was I suppose to get it from documentation