Maciej Piechotka

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  1. HDMI doesn't seem to work - no signal

    Sorry - it looks like I misread the code. HDMI HPD needs to be set out output and set to 1 when active.
  2. HDMI doesn't seem to work - no signal

    @jpeyron Setting aside that hdmi-in sample doesn't really use HDMI HPD it fails to generate bitstream: [Place 30-58] IO placement is infeasible. Number of unplaced terminals (4) is greater than number of available sites (0). The following are banks with available pins: IO Group: 0 with : SioStd: LVCMOS18 VCCO = 1.8 Termination: 0 TermDir: BiDi RangeId: 1 Drv: 12 has only 0 sites available on device, but needs 4 sites. Term: DDC_scl_io Term: DDC_sda_io Term: IIC_0_scl_io Term: and IIC_0_sda_io [Place 30-374] IO placer failed to find a solution Below is the partial placement that can be analyzed to see if any constraint modifications will make the IO placement problem easier to solve. +-------------------------------------------------------------------------------------------------------------------------------------------------------------------------+ | IO Placement : Bank Stats | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | Id | Pins | Terms | Standards | IDelayCtrls | VREF | VCCO | VR | DCI | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | 0 | 0 | 0 | | | | | | | | 13 | 0 | 0 | | | | | | | | 34 | 50 | 11 | LVCMOS33(11) | | | +3.30 | YES | | | 35 | 50 | 29 | LVCMOS33(21) TMDS_33(8) | | | +3.30 | YES | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ | | 100 | 40 | | | | | | | +----+-------+-------+------------------------------------------------------------------------+------------------------------------------+--------+--------+--------+-----+ IO Placement: +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | BankId | Terminal | Standard | Site | Pin | Attributes | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 34 | btns_4bits_tri_i[0] | LVCMOS33 | IOB_X0Y9 | R18 | | | | btns_4bits_tri_i[1] | LVCMOS33 | IOB_X0Y1 | P16 | | | | btns_4bits_tri_i[2] | LVCMOS33 | IOB_X0Y14 | V16 | | | | btns_4bits_tri_i[3] | LVCMOS33 | IOB_X0Y36 | Y16 | | | | sws_4bits_tri_i[1] | LVCMOS33 | IOB_X0Y2 | P15 | | | | sws_4bits_tri_i[2] | LVCMOS33 | IOB_X0Y41 | W13 | | | | sws_4bits_tri_i[3] | LVCMOS33 | IOB_X0Y32 | T16 | | | | vga_b[0] | LVCMOS33 | IOB_X0Y21 | P20 | | | | vga_g[1] | LVCMOS33 | IOB_X0Y22 | N20 | | | | vga_hs | LVCMOS33 | IOB_X0Y23 | P19 | | | | vga_vs | LVCMOS33 | IOB_X0Y49 | R19 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ | 35 | TMDS_clk_p | TMDS_33 | IOB_X0Y74 | H16 | | | | TMDS_clk_n | TMDS_33 | IOB_X0Y73 | H17 | | | | TMDS_data_p[0] | TMDS_33 | IOB_X0Y92 | D19 | | | | TMDS_data_n[0] | TMDS_33 | IOB_X0Y91 | D20 | | | | TMDS_data_p[1] | TMDS_33 | IOB_X0Y98 | C20 | | | | TMDS_data_n[1] | TMDS_33 | IOB_X0Y97 | B20 | | | | TMDS_data_p[2] | TMDS_33 | IOB_X0Y96 | B19 | | | | TMDS_data_n[2] | TMDS_33 | IOB_X0Y95 | A20 | | | | HDMI_OEN[0] | LVCMOS33 | IOB_X0Y87 | F17 | * | | | hdmi_hpd_tri_o[0] | LVCMOS33 | IOB_X0Y90 | E18 | | | | leds_4bits_tri_io[0] | LVCMOS33 | IOB_X0Y54 | M14 | | | | leds_4bits_tri_io[1] | LVCMOS33 | IOB_X0Y53 | M15 | | | | leds_4bits_tri_io[2] | LVCMOS33 | IOB_X0Y99 | G14 | | | | leds_4bits_tri_io[3] | LVCMOS33 | IOB_X0Y93 | D18 | | | | sws_4bits_tri_i[0] | LVCMOS33 | IOB_X0Y61 | G15 | * | | | vga_b[1] | LVCMOS33 | IOB_X0Y85 | M20 | | | | vga_b[2] | LVCMOS33 | IOB_X0Y80 | K19 | | | | vga_b[3] | LVCMOS33 | IOB_X0Y72 | J18 | | | | vga_b[4] | LVCMOS33 | IOB_X0Y64 | G19 | | | | vga_g[0] | LVCMOS33 | IOB_X0Y71 | H18 | | | | vga_g[2] | LVCMOS33 | IOB_X0Y82 | L19 | | | | vga_g[3] | LVCMOS33 | IOB_X0Y79 | J19 | | | | vga_g[4] | LVCMOS33 | IOB_X0Y65 | H20 | | | | vga_g[5] | LVCMOS33 | IOB_X0Y69 | F20 | | | | vga_r[0] | LVCMOS33 | IOB_X0Y86 | M19 | | | | vga_r[1] | LVCMOS33 | IOB_X0Y81 | L20 | | | | vga_r[2] | LVCMOS33 | IOB_X0Y66 | J20 | | | | vga_r[3] | LVCMOS33 | IOB_X0Y63 | G20 | | | | vga_r[4] | LVCMOS33 | IOB_X0Y70 | F19 | | +--------+----------------------+-----------------+----------------------+----------------------+----------------------+ [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure. [Common 17-69] Command failed: Placer could not place all instances
  3. HDMI doesn't seem to work - no signal

    I tried to use HDMI input but I cannot get it to work. I initialize the GPIO for HDMI HPD and HDMI OUT EN. Set the latter to 0. However HDMI HPD is 0 all the time - even if I plug the cable. The host doesn't seem to recognize connection either. Am I missing something? test.pdf
  4. [DRC NSTD-1] and [DRC UCIO-1] when generating bitstream with HDMI on Zybo

    @jpeyron Thanks. Using Zynq PS worked as well.
  5. [DRC NSTD-1] and [DRC UCIO-1] when generating bitstream with HDMI on Zybo

    @jpeyron Thanks. That one seems to work for simple designs but for more complicated designs it seems to place clocks in incorrect positions but I start separate thread for it.
  6. [DRC NSTD-1] and [DRC UCIO-1] when generating bitstream with HDMI on Zybo

    @jpeyron I've attached tcl and wrapper. Please let me know if you need something else. test.tcl test_wrapper.v
  7. [DRC NSTD-1] and [DRC UCIO-1] when generating bitstream with HDMI on Zybo

    @jpeyron Any progress? It doesn't seem to work even with attached constraints: [DRC UCIO-1] Unconstrained Logical Port: 8 out of 12 logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: hdmi_in_data_p[2:0], hdmi_in_data_n[2:0], hdmi_in_clk_n, and hdmi_in_clk_p.
  8. Cannot connect to USB cable

    Ok. Problem was the emulated USB controller. I needed to switch to Q35/nec-xhci. I managed to get it working.
  9. Cannot connect to USB cable

    @jpeyron Yes - I have installed board files. I've checked that the project is set to Zybo board. On Xilinx forum they think this is problem with drivers.
  10. Cannot connect to USB cable

    Hmm. I can program FPGA but if I try to run using system debugger it immediately disconnects: :37:10 INFO : Jtag cable 'Digilent Zybo 210279A42857A' is selected. 19:37:10 INFO : 'jtag frequency' command is executed. 19:37:10 INFO : Sourcing of '/home/mpiechotka/test/test.sdk/test_wrapper_hw_platform_0/ps7_init.tcl' is done. 19:37:10 INFO : Context for 'APU' is selected. 19:37:10 INFO : Hardware design information is loaded from '/home/mpiechotka/test/test.sdk/test_wrapper_hw_platform_0/system.hdf'. 19:37:10 INFO : 'configparams force-mem-access 1' command is executed. 19:37:10 INFO : Context for 'APU' is selected. 19:37:10 INFO : 'stop' command is executed. 19:37:28 INFO : 'ps7_init' command is executed. 19:37:28 INFO : 'ps7_post_config' command is executed. 19:37:28 INFO : Context for processor 'ps7_cortexa9_0' is selected. 19:37:28 INFO : Processor reset is completed for 'ps7_cortexa9_0'. 19:37:29 INFO : Context for processor 'ps7_cortexa9_0' is selected. 19:37:29 ERROR : Memory write error at 0x100000. Invalid DAP ACK value: 0 19:37:29 INFO : ----------------XSDB Script---------------- connect -url tcp:127.0.0.1:3121 source /home/mpiechotka/test/test.sdk/test_wrapper_hw_platform_0/ps7_init.tcl targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent Zybo 210279A42857A"} -index 0 loadhw -hw /home/mpiechotka/test/test.sdk/test_wrapper_hw_platform_0/system.hdf -mem-ranges [list {0x40000000 0xbfffffff}] configparams force-mem-access 1 targets -set -nocase -filter {name =~"APU*" && jtag_cable_name =~ "Digilent Zybo 210279A42857A"} -index 0 stop ps7_init ps7_post_config targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent Zybo 210279A42857A"} -index 0 rst -processor targets -set -nocase -filter {name =~ "ARM*#0" && jtag_cable_name =~ "Digilent Zybo 210279A42857A"} -index 0 dow /home/mpiechotka/test/test.sdk/test/Debug/test.elf ----------------End of Script---------------- If I try to use gdb instead it fails in ps7_init: 19:40:18 WARN : Given XMD transaction timeout value is invalid. Using default value of 60000 milli seconds 19:40:18 WARN : Given XMD transaction timeout value is invalid. Using default value of 60000 milli seconds 19:40:18 WARN : Given XMD transaction timeout value is invalid. Using default value of 60000 milli seconds 19:40:18 ERROR : Unexpected error while launching program. com.xilinx.sdk.targetmanager.TMException: Cannot flush JTAG buffers at com.xilinx.sdk.targetmanager.internal.TM.connectToProcessor(TM.java:478) at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.runTargetSetup(XilinxAppLaunchConfigurationDelegate.java:503) at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.runApplication(XilinxAppLaunchConfigurationDelegate.java:616) at com.xilinx.sdk.debug.core.XilinxAppLaunchConfigurationDelegate.launch(XilinxAppLaunchConfigurationDelegate.java:309) at com.xilinx.sdk.debug.ui.XilinxAppLaunchDelegateWrapper.launch(XilinxAppLaunchDelegateWrapper.java:31) at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:885) at org.eclipse.debug.internal.core.LaunchConfiguration.launch(LaunchConfiguration.java:739)
  11. Cannot connect to USB cable

    Ok. I needed to connect to server via HW manager and decrease the JTAG frequency. For whatever reason the auto-selected one was too high.
  12. Cannot connect to USB cable

    @jpeyron It seems to be something more complicated. I tried to open it in HW manager and I got following error: open_hw_target INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Digilent/210279A42857A ERROR: [Labtools 27-2269] No devices detected on target localhost:3121/xilinx_tcf/Digilent/210279A42857A. Check cable connectivity and that the target board is powered up then use the disconnect_hw_server and connect_hw_server to re-register this hardware target. open_hw_target: Time (s): cpu = 00:00:03 ; elapsed = 00:00:17 . Memory (MB): peak = 6274.699 ; gain = 0.000 ; free physical = 13077 ; free virtual = 14425 ERROR: [Common 17-39] 'open_hw_target' failed due to earlier errors. ERROR: [Labtoolstcl 44-513] HW Target shutdown. Closing target: localhost:3121/xilinx_tcf/Digilent/210279A42857A The code in target seems to match the serial number of board: Found 1 device(s) Device: Zybo Product Name: Digilent Zybo User Name: Zybo Serial Number: 210279A42857 I reinstall the whole OS but w/out success.
  13. Cannot connect to USB cable

    @jpeyron Yes (well - via sudo but that shouldn't matter).
  14. Cannot connect to USB cable

    @jpeyron No. Last time when I installed as root Vivado HLS did not work. With regard to system -i t is almost pure CentOS (I don't think I installed anything outside tools) installation in VM. I installed the digilent utils/libraries from rpm. I tried to run install script from vivado (as root). I'm not sure what else might be relevant.
  15. Error [DRC PDRC-34] when trying to use dvi2rgb on Vivado 2017.4

    @JColvin The problem with section 3 and 6 is that they refer to TMDS Clk only. However the problem seems to be in RefClock which is only documented as 200 MHz in section 4 and 5 - signal is literally described as "200 MHz reference clock" in signal description... It might be that someone more familiar with FPGAs and/or DVI might've deduce it from documentation but after reading 3 times after I know what the solution is I have no idea how was I suppose to get it from documentation