@jpeyron I know those documents. However after reading them many times I find them both too detailed and underspecified. For example:
I assume the format is RGB not RBG (as documented) on output. Otherwise both IP and interface are misnamed.
It still don't answer if the VSYNC is kept high through the whole period or is it a pulse?
With regard to VDMA what format is it stored in? I assume it is just a bitmap but are RGB aligned to 1 byte (3 byte addressing) or 4 bytes [After a though - AXI is power of 2 so it must be 32-bit aligned]?
What happens if the data is shorter then VSIZE or HSIZE [EDIT: It seems that it sends VDMAIntErr]? I assume it goes to next stride (EDIT: no it does not] but is it possible to recover original resolution or do I need to count manually?
What is memory coherence when using SoC HS Axi by VDMA. I assume, though I haven't found it documented anywhere, that HS AXI will reply on BRESP after it hits data accessible by other ports and CPU (assuming that non-cached access is used). In other words if there is write W1 and read R1 the R1 happens-after W1 (in memory model sense) iff BRESP for W1 has been issued. But does the VDMA waits synchronously on it before proceeding to next frame [i.e. is there a system membar between frames]?