Thausikan
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Topics posted by Thausikan
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Question: How to connect DMA with microblaze ?
- Awaiting best answer
- 0 votes
- 6 answers
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Question: Axi Performance monitor for 10G/25G Ethernet SubSystem
- Awaiting best answer
- 0 votes
- 1 answer
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Question: AXI EthernetLite IP usage in Avnet Kintex Ultrascale board
- Awaiting best answer
- 0 votes
- 1 answer
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Question: Place design Error-Rule Violation[23-20] in Vivado
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- 0 votes
- 3 answers
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Question: LWIP:itoa Function for FPGA- How to increase the buffer size ?
- Awaiting best answer
- 0 votes
- 7 answers
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Question: Ethernetlite design (LWIP): Whether AXI UART IP is mandatory ?
- Awaiting best answer
- 0 votes
- 4 answers
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Question: Implementation of LWIP Echo Server (Axi ETHERNETLITE) without using AXI UARTLITE
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- 0 votes
- 1 answer
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- 7 answers
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Question: How to communicate with the System via Xilinx Platform cable II [JTAG] using Python library?
- Awaiting best answer
- 0 votes
- 1 answer
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Question: How to connecte IBUFDS(LVDS in) single ended output with microblaze and FIFO setup
- Awaiting best answer
- microblaze
- lvds
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- 0 votes
- 1 answer
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Question: Aurora_TX and RX Loopback Test result Fail Options
- Awaiting best answer
- microblaze
- vivao ip
- (and 2 more)
- 0 votes
- 1 answer
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sdk Question: Returning Improper Sequence values in XSDK From HLS IP
- Awaiting best answer
- 0 votes
- 1 answer
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Question: For steam data communication between HLS IP and SDK
- Awaiting best answer
- hls
- ip integrator
- (and 2 more)
- 0 votes
- 1 answer