Thausikan

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Everything posted by Thausikan

  1. Hi, I am using ZCU102 board (Zynq Ultrascale+ MPSoC). I am sending the data (data packet) generating from custom HLS IP to 10G High speed subsystem without using AXI DMA. I am able to monitor the data in Wireshark but i want to measure the performance of the design. So, i have added Axi Performance monitor IP`s block into our design. The platform used for Performance monitor is XSDK. While compiling the XSDK, the performance count of each read and write axis its showing "zero". Please anyone guide me how to implement the design with Axi Performance monitor. I have attached the screenshot what we tried.
  2. Hi, I am trying to use EthernetLite IP on KU board. In this IP the MII is used, but in KU040 board its mentioned as RGMII instead of MII. So Can I use this Ethernetlite iP on KU040? Plz give me suggestions. Thanks,
  3. >>Apparently, the "gt_reset" pin in your toplevel design wants to drive 1.8 V. Yes, Already I have assigned 1.8 volt for gt_reset pin as per the board files. But still the error is existing.
  4. I am getting the below error during implementation in AVENT Kintex Ultra scale (ku040) as per the data sheet. All the DDR pin specifications and I/O standards have checked and its correct but even its displaying below error message. [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run. [DRC 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 45. For example, the following two ports in this bank have conflicting VCCOs: ddr4_sdram_dqs_t[2] (DIFF_POD12_DCI, requiring VCCO=1.200) and gt_reset (LVCMOS18, requiring VCCO=1.800) Please anyone guide me.
  5. Thanks . I am getting the data in Hercules only upto length 90. Afterthat in XSDK console, i am getting message :"no space in tcp_sndbuf". I am unable to add this line code "xil_printf("DEBUG: %s %d %s\n", __PRETTY__FUNCTION, __LINE__, outbuffer )". I am getting an error message "undeclared". So, i have modified the code little bit. static char buffer[50]; err_t recv_callback(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err) { int i,j,Status; int len; Status=aurora_rx_main(); ///FUNCTION CALL for(i=0;i<50;i++) { xil_printf("%d,", DestinationBuffer[i]); } if (!p) { tcp_close(tpcb); tcp_recv(tpcb, NULL); return ERR_OK; } /* indicate that the packet has been received */ tcp_recved(tpcb, p->len); for (j=0; j <= 50 && (tcp_sndbuf(tpcb) > sizeof(buffer)); ++j) { len = sprintf(buffer, "%d,", DestinationBuffer[j]); /* xil_printf("\n"); xil_printf(" length : %d", len); xil_printf(" buffer : %s", buffer); */ err = tcp_write(tpcb,buffer,len, 1); tcp_sent( tpcb, NULL ); tcp_output(tpcb); } if(j<50) { xil_printf("no space in tcp_sndbuf\n\r"); //break; } /* free the received pbuf */ pbuf_free(p); return ERR_OK; } err_t accept_callback(void *arg, struct tcp_pcb *newpcb, err_t err) { static int connection = 1; /* set the receive callback for this connection */ tcp_recv(newpcb, recv_callback); /* just use an integer number indicating the connection id as the callback argument */ tcp_arg(newpcb, (void*)connection); /* increment for subsequent accepted connections */ connection++; return ERR_OK; } last value i am getting in negative. Why can clarify me ?
  6. Thanks for your response. I have changed my code according to your format. Edited code static char buf[35] = {0}; int howMuchToStillWrite=0; char *itoa(long int val, int base){ int i = 34; for(; val && i ; --i, val /= base) buf[i] = "0123456789abcdef"[val % base]; return &buf[i+1]; } err_t recv_callback(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err) { int i,j,Status; int len; //char outbuffer[20]; Status=aurora_rx_main(); ///FUNCTION CALL for(i=0;i<35;i++) { xil_printf("%d\n", DestinationBuffer[i]); } int base=10; // here 10 means decimal char *result={0}; if (!p) { tcp_close(tpcb); tcp_recv(tpcb, NULL); return ERR_OK; } /* indicate that the packet has been received */ tcp_recved(tpcb, p->len); for (j=0; j <= 35 && (tcp_sndbuf(tpcb) > 35);j++) { result= itoa(DestinationBuffer[j],base); // err = tcp_write(tpcb,",",1,1); err = tcp_write(tpcb,result,35,1); // tcp_sent( tpcb, NULL ); // tcp_output(tpcb); } if (err != ERR_OK) { //How much still needs to be written out.. howMuchToStillWrite = 35 -j; } else { tcp_sent( tpcb, NULL ); tcp_output(tpcb); } /* free the received pbuf */ pbuf_free(p); return ERR_OK; } Hercules Window, I have attached. I am getting some constant ASCII values. Again i have pasted your modifies for cross verification.
  7. Sorry, I can`t understand your point. I am stuck in this problem for past 15 days. How to increase TCP send buffer size ?? Please follow the below i have posted same thing with Screen shots. https://forums.xilinx.com/t5/Embedded-Processor-System-Design/LWIP-echo-Example-data-printing-in-Hercules-with-Junk-values/m-p/900266#M42254 https://forums.xilinx.com/t5/Embedded-Development-Tools/KINTEX-KC705-LWIP-Ethernetlite-recv-callback-Function/td-p/895443 Actually, Data is generated from DAQ board and passed to KC705 board through optical cable. In KC705, received data is stored in destination buffer. Now, i am trying to read that data stored in destination buffer in PC through Ethernetlite (LWIP Echo template). Please clarify me step by step. Thanks
  8. Hi, I have followed your steps. But again one doubt. Same thing I have followed :created an ethernet project with the axi-uart and export it to SDK. ´╗┐Then created an application with the LWiP echo server. Then i went back to vivado and edited the bock design removing the uart. I then deleted and re-generated the wrapper. I then generated a bitstream and re-exported the hardware including the bitstream. With axi-uart , i have generated hardware platform_0 Without axi-uart , i have generated hardware platform_1 I need to run this design only without axi-uart. So my doubt is which hardware platform i need to select while programming the FPGA. Without axi-uart design, i am able to get data only if i select hardware platform_0. hardware platform_1 is not giving any output. Then what difference is in design.
  9. static char buf[32] = {0}; // Globally declared char* itoa(int val, int base) { int i = 30; for(; val && i ; --i, val /= base) buf[i] = "0123456789abcdef"[val % base]; return &buf[i+1]; } I am working with Xilinx Ethernetlite (lwip) design. With LWIP Echo template, I am able to make communication between FPGA board and PC (hercules). The issue is in hercules or in itoa Function. I am unable to make sure. In Hercules, to print the data i am doing itoa conversion Function in echo file. Only if buf size is 32. I am able to read the properly. If i increase the buf size is 1024. I am not able to read the data in Herceuls. err_t recv_callback(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err) { int i,j,Status; Status=aurora_rx_main(); ///FUNCTION CALL for(i=0;i<100;i++) { xil_printf("%d\n", DestinationBuffer[i]); } int base=10; // here 10 means decimal char *result={0}; if (!p) { tcp_close(tpcb); tcp_recv(tpcb, NULL); return ERR_OK; } /* indicate that the packet has been received */ tcp_recved(tpcb, p->len); if (tcp_sndbuf(tpcb) > 100) //if (tcp_sndbuf(tpcb) <= p->len) { for (j=0;j<=100;j++) { result= itoa(DestinationBuffer[j],base); err = tcp_write(tpcb,",",1,1); err = tcp_write(tpcb,result,100,1); // Unable to read the 100 values in Hercules. tcp_sent( tpcb, NULL ); tcp_output(tpcb); } } else //xil_printf("no space in tcp_sndbuf\n\r"); /* free the received pbuf */ pbuf_free(p); return ERR_OK; }
  10. First, Thanks for your kind response. >>It appears you asked xilinx the creators of the LWiP. Yes, still they have not responded. Ok, I understood your point. But one more doubt, if i need to remove all uses and #includes of the uartlite in the echo_server template then i need to access the "LWIP Echo server Template". But i am not able to choose the "LWIP Echo server Template" from XSDK Please look the above message. Its showing an error messgae " This application requires a Uart IP in the hardware". Then how please suggest me.
  11. I am using KC705 board, and working with vivado 2015.4. In current design, i have implemented the below process using the AXI UARTLITE. 1. Counter data (Binary Counter IP) from Kintex DAQ board (Part Number : XC7k160tffg676-2) is passing to the KINTEX KC705 board through optical cable. No issue. I am able to read the data in KINTEX KC705 through AXI FIFO 2. KC705 board will pass the data From FIFO to PC through LWIP Echo server, where i can able to read the data in Hercules. Same Process should be done without using AXI UARTLITE module. So, I have removed AXI - UARTLITE IP in my design, and generated the bit stream. After lunching the hardware and export the hardware, i am unable to create application template (LWIP echo server). Its showing an error messgae " This application requires a Uart IP in the hardware". Please anyone suggest me. How I can use LWIP without using AXI Uartlite. Can anyone suggest me please.
  12. Hi, In current design, i have implemented the below process using the AXI UARTLITE. 1. Counter data (Binary Counter IP) from Kintex DAQ board (Part Number : XC7k160tffg676-2) is passing to the KINTEX KC705 board through optical cable. No issue. I am able to read the data in KINTEX KC705 through AXI FIFO. Both controls and data transfer should happen over Ethernet. 2. KC705 board will pass the data From FIFO to PC through LWIP Echo server, where i can able to read the data in Hercules. Same Process should be done without using AXI UARTLITE module. Please anyone suggest me how to modify the design.
  13. Yes, i have tried with different lengths including p->len =40,54,64 beyond 32. Same thing , if i go beyond p->len =32, in hercules or in python i am getting junk values. Please find the attachment. (for p->len =64)
  14. if i set p->len =32 no junk values but if i go beyond 32 i am getting Junk values . why so. Please explain me the process i am new to networking design. err = tcp_write(tpcb,result,32,1); }
  15. Thanks for your response. Now i am able to read the data in PC through Hercules. But in Hercules or in Python files, i am getting same error (some junk values are printing). Can anyone explain me how tcp_write function works. static char buf[64] = {0}; //extern u32 DestinationBuffer[50]; int transfer_data() { return 0; } char *itoa(int val, int base){ int i = 30; for(; val && i ; --i, val /= base) buf[i] = "0123456789abcdef"[val % base]; return &buf[i+1]; } err_t recv_callback(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err) { int i,j,Status; Status=aurora_rx_main(); ///FUNCTION CALL for(i=0;i<50;i++) { xil_printf("%d,", DestinationBuffer[i]); } int base=10; // here 10 means decimal char *result={0}; if (!p) { tcp_close(tpcb); tcp_recv(tpcb, NULL); return ERR_OK; } /* indicate that the packet has been received */ tcp_recved(tpcb, p->len); if (tcp_sndbuf(tpcb) > 50) { for (j=0;j<=50;j++) { result= itoa(DestinationBuffer[j],base); err = tcp_write(tpcb,",",1,1); err = tcp_write(tpcb,result,32,1); } } else xil_printf("no space in tcp_sndbuf\n\r"); /* free the received pbuf */ pbuf_free(p); return ERR_OK; } Please tell me how to increase p->len size or else how to clear the junk values
  16. I need to transfer the data from the kc705 board to the PC using LWIP Echo Server. Design Flow as follows as below: 1. Counter data from Kintex DAQ board (Part Number : XC7k160tffg676-2) is passing to the KINTEX KC705 board through optical cable [Completed] 2. KINTEX KC705 board Should pass the data to PC through LWIP Echo server [Unable to pass the received data to TCP]. I am new to Ethernet Design [Network] so apology me for asking silly question. For me doubt in Echo Coding part. /////////////////////Function to receive Data in KC705 from DAQ board ////////////// int RxReceive (XLlFifo *InstancePtr, u32* DestinationAddr) { int i; //int Status; u32 RxWord; static u32 ReceiveLength; ReceiveLength = (XLlFifo_iRxGetLen(InstancePtr))/WORD_SIZE; /* Start Receiving */ if(ReceiveLength>0) { //xil_printf("@@@@@@@@@ "); for ( i=0; i < ReceiveLength; i++) { RxWord = 0; RxWord = XLlFifo_RxGetWord(InstancePtr); *(DestinationAddr+i) = RxWord; //*(DestinationAddr+i) = 10; xil_printf("received data : %d\n\r",*(DestinationAddr+i)); } } return XST_SUCCESS; } How to pass that received data into TCP [tcp_write() function]. I have coded Please correct if i am wrong. extern u32 DestinationBuffer[1024]; // Globally Declared : Counter Values are stored in destination buffer. Those values i am passing to tx_func. That function is called in recv_callback. extern void tx_func(struct tcp_pcb *tpcb) { int i,Status; Status=aurora_rx_main(); for(i=0;i<1024;i++) { xil_printf("%d,",DestinationBuffer[i]); } tcp_write(tpcb, DestinationBuffer, 1024, 0); //////////////// tcp_write Function getting data from DestinationBuffer } err_t recv_callback(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err) { /* do not read the packet if we are not in ESTABLISHED state */ if (!p) { tcp_close(tpcb); tcp_recv(tpcb, NULL); return ERR_OK; } /* indicate that the packet has been received */ tcp_recved(tpcb, p->len); /* echo back the payload */ /* in this case, we assume that the payload is < TCP_SND_BUF */ tcp_recved(tpcb, p->len); { tx_func(tcp_pcb) } else xil_printf("no space in tcp_sndbuf\n\r"); /* free the received pbuf */ pbuf_free(p); return ERR_OK; }
  17. Hi, I am searching for the Python library like PY USB and Py Serial communication, for JTAG cable. I am trying to give input to the system using the Python code via Platform cable II [JTAG]. So , Can anyone share the Python code for the JTAG cable, or else please anyone suggest how to start this work.
  18. Hi, PRBS data from 1st board--> LVDS out (data)--> LVDS in (data)--->2nd board-> Aurora Tx (2nd board)-> Aurora Rx (1st board). Almost, i have completed the first part (1st board side), but in second part i dont know how to connect the IBUFDS(LVDS in) with microblaze and FIFO setup. Because IBUDS does not have AXI kind of connections. Please anyone guide ma.
  19. Hi, I have integrated simplex TX aurora block and simplex RX aurora blocks into a single design through a loop-back in order to make duplex mode. But while simulating the XSDK codes, TX length and RX length are mismatched. I am working with Kintex development DAQ board [xc7k160tffg676-2], and i have attached the BD design in which TX and RX are make into external. Where i am going wrong i don`t know, please point out and guide me. Please find the attachment of BD diagram. Thanks
  20. Hello, I've been doing a few beginner experiments with AXI peripherals and following some tutorials online on how to create AXI peripherals and implement on my Kintex board. So far, I've managed to successfully create a simple custom hardware block and connect it via AXI4-Lite. For counter program, Created a new design on Vivado includes AXI Stream data FIFO, AXI Stream FIFO, microblaze and aurora, and through in XSDK, I wrote C codes for counter program and executed. Its working Fine. Help : I need to add DMA into the counter design. So, How can i connect DMA with microblaze ? However: I have no idea at all on how to achieve this DMA data transfer via AXI4 to the microblaze working memory. Any Example design also help me. If anyone has, please share to me. I need to connect DMA with microblaze.
  21. Hi,Just start learning HLS and XSDk. Currently I am working with number series. My goal is to print number series sequentially as for "N" times in Tera Terminal. While compiling the program codes, its returning values but it is not in sequence. Expected result:2, 4, 8, 16,32,64,128,256,512,1024, But i am getting : 4,8,16,256,128,1024,16,64,512,64, (not in order) For more details refer this [link]: https://forums.xilinx.com/t5/Welcome-Join/Returning-only-Last-value-in-XSDK-From-HLS-IP-Instead-of-series/td-p/767236 void Numberseries1(ap_uint<32> seed, ap_uint<32> &dout) { #pragma HLS INTERFACE s_axilite port=seed bundle=a #pragma HLS INTERFACE s_axilite port=dout bundle=a #pragma HLS INTERFACE s_axilite port=return bundle=a ap_uint<32> reg[10]; int result=1; int i; for(i=0; i < 10;i++) #pragma HLS unroll factor=8 if (result<seed) { result *= 2; reg =result; dout= reg; } }
  22. Hi, Currently I'm working with micorblaze and Kintex 7 board, for Pseudo_random bit sequence (PRBS) function. I have created HLS IP (PRBS), integrated IP with vivado and exported it to SDK. But in SDK, i am getting only "Single bit" value instead of sequence of random bits. Please anyone guide me. What`s wrong in my coding? Need help from anyone. I need to get non-stop stream of random bits out of the IP and to display on Tera Terminal through XSDK. Hls Source code #include <stdint.h> #include <stdio.h> #include "ap_cint.h" int PRBS_prj(int bit) { #pragma HLS INTERFACE s_axilite port=return bundle=a int start_state = 0xCD; int lfsr = start_state; unsigned period = 0; do { /* taps: 3, 2 and 1 ; feedback polynomial: x^3 + x^2 + 1 */ bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 4) ) & 1; printf("%d", bit); lfsr = (lfsr >> 1) | (bit << 7); ++period; } while (lfsr != start_state); return bit; } or int main(void) { static int lfsr = 0x3425u; unsigned int mask = 0xF0; int bit; /* Must be 16bit to allow bit<<15 later in the code */ //taps: 16 14 13 11; feedback polynomial: x^16 + x^14 + x^13 + x^11 + 1 bit = ((lfsr >> 0) ^ (lfsr >> 2) ^ (lfsr >> 3) ^ (lfsr >> 5) ) & 1; lfsr = (lfsr >> 1) | (bit << 15); for (mask = 0xF0; mask; mask >>= 1) putchar('0' + !!(lfsr & mask)); return lfsr; }