Thausikan

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  1. Hi, I am using ZCU102 board (Zynq Ultrascale+ MPSoC). I am sending the data (data packet) generating from custom HLS IP to 10G High speed subsystem without using AXI DMA. I am able to monitor the data in Wireshark but i want to measure the performance of the design. So, i have added Axi Performance monitor IP`s block into our design. The platform used for Performance monitor is XSDK. While compiling the XSDK, the performance count of each read and write axis its showing "zero". Please anyone guide me how to implement the design with Axi Performance monitor. I have attached the
  2. Hi, I am trying to use EthernetLite IP on KU board. In this IP the MII is used, but in KU040 board its mentioned as RGMII instead of MII. So Can I use this Ethernetlite iP on KU040? Plz give me suggestions. Thanks,
  3. >>Apparently, the "gt_reset" pin in your toplevel design wants to drive 1.8 V. Yes, Already I have assigned 1.8 volt for gt_reset pin as per the board files. But still the error is existing.
  4. I am getting the below error during implementation in AVENT Kintex Ultra scale (ku040) as per the data sheet. All the DDR pin specifications and I/O standards have checked and its correct but even its displaying below error message. [Vivado_Tcl 4-23] Error(s) found during DRC. Placer not run. [DRC 23-20] Rule violation (BIVC-1) Bank IO standard Vcc - Conflicting Vcc voltages in bank 45. For example, the following two ports in this bank have conflicting VCCOs: ddr4_sdram_dqs_t[2] (DIFF_POD12_DCI, requiring VCCO=1.200) and gt_reset (LVCMOS18, requiring VCCO=1.800) Please anyone g
  5. Thanks . I am getting the data in Hercules only upto length 90. Afterthat in XSDK console, i am getting message :"no space in tcp_sndbuf". I am unable to add this line code "xil_printf("DEBUG: %s %d %s\n", __PRETTY__FUNCTION, __LINE__, outbuffer )". I am getting an error message "undeclared". So, i have modified the code little bit. static char buffer[50]; err_t recv_callback(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err) { int i,j,Status; int len; Status=aurora_rx_main(); ///FUNCTION CALL for(i=0;i<50;i++)
  6. Thanks for your response. I have changed my code according to your format. Edited code static char buf[35] = {0}; int howMuchToStillWrite=0; char *itoa(long int val, int base){ int i = 34; for(; val && i ; --i, val /= base) buf[i] = "0123456789abcdef"[val % base]; return &buf[i+1]; } err_t recv_callback(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err) { int i,j,Status; int len; //char outbuffer[20]; Status=aurora_rx_main(); ///FUNCTION CALL for(i=0;i<35;i++) { xil_printf("%d\n", DestinationBuffer[i]);
  7. Sorry, I can`t understand your point. I am stuck in this problem for past 15 days. How to increase TCP send buffer size ?? Please follow the below i have posted same thing with Screen shots. https://forums.xilinx.com/t5/Embedded-Processor-System-Design/LWIP-echo-Example-data-printing-in-Hercules-with-Junk-values/m-p/900266#M42254 https://forums.xilinx.com/t5/Embedded-Development-Tools/KINTEX-KC705-LWIP-Ethernetlite-recv-callback-Function/td-p/895443 Actually, Data is generated from DAQ board and passed to KC705 board through optical cable. In KC705, received data is stored
  8. Hi, I have followed your steps. But again one doubt. Same thing I have followed :created an ethernet project with the axi-uart and export it to SDK. ´╗┐Then created an application with the LWiP echo server. Then i went back to vivado and edited the bock design removing the uart. I then deleted and re-generated the wrapper. I then generated a bitstream and re-exported the hardware including the bitstream. With axi-uart , i have generated hardware platform_0 Without axi-uart , i have generated hardware platform_1 I need to run this design only without axi-uart. So
  9. static char buf[32] = {0}; // Globally declared char* itoa(int val, int base) { int i = 30; for(; val && i ; --i, val /= base) buf[i] = "0123456789abcdef"[val % base]; return &buf[i+1]; } I am working with Xilinx Ethernetlite (lwip) design. With LWIP Echo template, I am able to make communication between FPGA board and PC (hercules). The issue is in hercules or in itoa Function. I am unable to make sure. In Hercules, to print the data i am doing itoa conversion Function in echo file. Only if buf size is 32. I am able to read the properly. If i increase the buf
  10. First, Thanks for your kind response. >>It appears you asked xilinx the creators of the LWiP. Yes, still they have not responded. Ok, I understood your point. But one more doubt, if i need to remove all uses and #includes of the uartlite in the echo_server template then i need to access the "LWIP Echo server Template". But i am not able to choose the "LWIP Echo server Template" from XSDK Please look the above message. Its showing an error messgae " This application requires a Uart IP in the hardware". Then how please suggest me.
  11. I am using KC705 board, and working with vivado 2015.4. In current design, i have implemented the below process using the AXI UARTLITE. 1. Counter data (Binary Counter IP) from Kintex DAQ board (Part Number : XC7k160tffg676-2) is passing to the KINTEX KC705 board through optical cable. No issue. I am able to read the data in KINTEX KC705 through AXI FIFO 2. KC705 board will pass the data From FIFO to PC through LWIP Echo server, where i can able to read the data in Hercules. Same Process should be done without using AXI UARTLITE module. So, I have removed AXI - UARTLITE IP
  12. Hi, In current design, i have implemented the below process using the AXI UARTLITE. 1. Counter data (Binary Counter IP) from Kintex DAQ board (Part Number : XC7k160tffg676-2) is passing to the KINTEX KC705 board through optical cable. No issue. I am able to read the data in KINTEX KC705 through AXI FIFO. Both controls and data transfer should happen over Ethernet. 2. KC705 board will pass the data From FIFO to PC through LWIP Echo server, where i can able to read the data in Hercules. Same Process should be done without using AXI UARTLITE module. Please anyone suggest me ho
  13. Yes, i have tried with different lengths including p->len =40,54,64 beyond 32. Same thing , if i go beyond p->len =32, in hercules or in python i am getting junk values. Please find the attachment. (for p->len =64)
  14. if i set p->len =32 no junk values but if i go beyond 32 i am getting Junk values . why so. Please explain me the process i am new to networking design. err = tcp_write(tpcb,result,32,1); }
  15. Thanks for your response. Now i am able to read the data in PC through Hercules. But in Hercules or in Python files, i am getting same error (some junk values are printing). Can anyone explain me how tcp_write function works. static char buf[64] = {0}; //extern u32 DestinationBuffer[50]; int transfer_data() { return 0; } char *itoa(int val, int base){ int i = 30; for(; val && i ; --i, val /= base) buf[i] = "0123456789abcdef"[val % base]; return &buf[i+1]; } err_t recv_callback(void *arg, struct tcp_pcb *tpcb, struct pbuf *p, err_t err) {