• Content Count

  • Joined

  • Last visited

About ntm

  • Rank

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. I'm looking for an Arduino-style hello word example that will run on a Microblaze core, implemented on a Nexys4DDR board. I'm using Vivado. In terms of a (C/C++) design, I'm thinking about read in from the ADC and blink a light fast or slow depending on the ADC value. While I know you can do this with verilog, I'd like to develop my skills with soft-core processors. If you know of a basic entry-level FPGA+microblaze design tutorial like this I'd be grateful! Update, searching through the forums yielded these references: - https://reference.digilentinc.com/vivado/gett
  2. I'm working on small designs for a computer architecture course with Nexys4 DDR boards. Vivado seems pretty slow, maybe 3-4 minutes to go from verilog files to bitstream file on a Windows 8, Intel i5, 2.2GHz, 8GB RAM. 1. Is this "compile" time normal? 2. Are there ways to skip the optimization steps to make a less-efficient (space/run-speed wise) design, eg, is there a "gcc -O0 file.c" equivalent? 3. Is there any (time/speed) advantage to running Vivado commands in the shell rather than via GUI?
  3. I'm working on what should be a simple 7-segment display driver for the Nexys4DDR. Right now I've got a module that should transfer a 9:0 one-hot encoding to 7-segment display digits. I'm using the Nexys4's switches to simulate the 1-hot and the AN[0] display digit to check the module. So far as I can tell Vivado refuses to let me hard-code the value 1'b0 to AN[0]. This seems odd. I either get the "an0 doesn't have a real value and you're about the smoke the board" error from write bitstream, and also sometimes complaints about accessing a single array element (ie, working with just AN[0]
  4. I'm getting started with a Nexys4DDR board. Havn't used Vivado before - have used ISE for a while. In the Nexys 4 DDR documentation, the Xilinx FPGA is specified as (Xilinx part number XC7A100T-1CSG324C). When I create a new design in Vivado, the part number above doesn't match the available options. I read somewhere that the speed grade of the device is -3, and the number of flip-flops (DIgilent says 15.8k logic slices*8 flip-flops = 126k flip-flops) seems to match the xc7a100tcsg324-3 device, which has 126800 flip-flops and 240 dsp slices. I don't really like "guess and co