Hi Folks,
I am working with Xilinx Zynq7020 SOC Chip.
Also, I am using Digilent JTAG-HS3 Jtag.
I made design in vivado 2015.2 and HLS IP block also made in Vivado HLS 2015.2, design is checked in SDK 2015.2 is working fine.
Presently, i upgraded to 2016.4 vivado package and upgraded the 2015.2 design to 2016.4.
validates the design and generate bit stream in 2016.4.
Running the design in SDK 2016.4 with source (C) files.
Initially i restored the image into DDR3 physical address location, in SDK Log showing restore successfully,Afte
