Miguel

Members
  • Content Count

    7
  • Joined

  • Last visited

  • Days Won

    2

Miguel last won the day on June 4 2017

Miguel had the most liked content!

About Miguel

  • Rank
    Newbie

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. Hello, @D@n! Thank you VERY MUCH!!!!!! Problem with terrible signal is solved!!!!!(code is bellow) but Some times I have a problem with PmodDA4, I have to switch my sw (Comand bits), then it works normal... It is not very big problemfor me now, but it is better to solve it (in my opinion) word_countp: process(sclk0) begin if rising_edge(sysclk) then if word_count < "10011100001111" then word_count <= word_count + 1; else word_count <=(others => '0'); end if; if word_count < "11111001111" then sync0 <= '1'; else sync0 <= '0'; end if; if sync0 = '0' then if count_2 < 249 then count_2 <= count_2 + 1; pout <= pdata(31 - number); else count_2 <= 0; number <= number + 1; end if; else count_2 <= 0; end if; if number > 31 then number <= 0; end if; pdata <= "0000" & sw(7) & sw(6) & sw(5) & sw(4) & "0000" & DAC_1 & "00000001"; end if; end process word_countp;
  2. The problem which I found is: I always send pdata <= "0000" & "0000" & "0000" & DAC_1 & "00000001"; where DAC_1 is std_logic_vector(11 downto 0), I see analog signal from A chanel (Ground - GND, Positive - A) on the digital oscilloscope, but I see terrible result. But if I connect the second oscilloscope channel to the sclk - wave is really good. Some times DAC does not work, so I have to send pdata <= "0000" & "0100" & "0000" & DAC_1 & "00000001", then toutch by the second oscilloscope channel positive wire SYNC then pdata <= "0000" & "0000" & "0000" & DAC_1 & "00000001" and it works. What I do wrong? Should I send constant C bits always? and what sequence?
  3. It works. Code is bellow. I obtain only one analog signal (between GND and Pin A). If somebody find some mistakes, please write about it! Problem was: all things had to be at falling_edge of the sclk0. library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.ALL; use ieee.numeric_std.all; entity pmodad1_test is port( sysclk : in std_logic; -- 100MHz clock ja : inout std_logic_vector(7 downto 0); sw : in std_logic_vector(7 downto 0); ); end pmodad1_test; architecture Behavioral of pmodad1_test is signal data_0 : std_logic_vector(11 downto 0) := (others=>'0'); --DAC_PROG signal count: STD_LOGIC_VECTOR(27 downto 0) := X"0000000"; signal count2: STD_LOGIC_VECTOR(11 downto 0) := X"001"; signal word_count: STD_LOGIC_VECTOR(5 downto 0) := "000000"; signal sclk0 : STD_LOGIC; signal pout : STD_LOGIC; signal sync0 : STD_LOGIC := '0'; -- signal data: STD_LOGIC_VECTOR(11 downto 0) := X"000"; signal pdata: STD_LOGIC_VECTOR(31 downto 0) := X"00000000"; begin counterp: process(sysclk) begin if rising_edge(sysclk) then count <= count + 1; end if; end process counterp; --************************************************************************************************ sclkp: process(sysclk, count) begin if rising_edge(sysclk) then if btnl = '1' then -- Use the same freq for both LEDs and sync sclk0 <= count(25); -- Divide 100 MHz / 2^25 => "human" freq else sclk0 <= count(5); -- Divide 100 MHz / 32 = 3.125 MHz end if; end if; end process sclkp; --************************************************************************************************ -- Word bits counter: 40 = 32 bits sync + 8 void bits word_countp: process(sclk0) begin if falling_edge(sclk0) then if word_count = "101000" then word_count <= "000000"; else word_count <= word_count + 1; end if; end if; end process word_countp; --************************************************************************************************ -- Sync signal signal_syncp: process(sclk0, word_count) begin if falling_edge(sclk0) then if word_count = "000000" then sync0 <= '0'; elsif word_count = "100000" then sync0 <= '1'; end if; end if; end process signal_syncp; --************************************************************************************************ signal_shiftp: process(sclk0, word_count, sw, count2) begin if falling_edge(sclk0) then if word_count = "101000" then pdata <= "0000" & sw(7) & sw(6) & sw(5) & sw(4) & sw(3) & sw(2) & sw(1) & sw(0) & data_0 & "00000001"; else pdata <= pdata(30 downto 0) & pdata(31); end if; end if; end process signal_shiftp; --************************************************************************************************ -- Data transmission process spip: process(sclk0) begin if falling_edge(sclk0) then if sync0 = '0' then pout <= pdata(31); -- Send the signal else pout <= '0'; end if; end if; end process spip; --************************************************************************************************ ja(0) <= sync0; -- SYNC ja(1) <= pout; -- DOUT ja(2) <= pout; -- Just duplicate DOUT ja(3) <= sclk0; -- SCLK end Behavioral;
  4. Dear Dan! Thank you for your quick answer! I can not send you a picture from the simulator, because it sends me some errors, so I cant "switch it on". But I work with oscilloscope, so you can see all signalls what I send to the PmodDA4. 1 - data_0 <= (others =>'1'), 4 Command Bits + 4 Address Bits are '0', and the last one is pout (0) <= '1'.
  5. Dear collegues! Thank you for your answers! I have found an example and rewrited it just a little bit (saw info from http://www.analog.com/media/en/technical-documentation/data-sheets/AD5628_5648_5668.pdf) , page 24. But it does not work...I do not obtain analog signals on the output of the pmodda4. pdata - is data for the output, it consists of: "0000" - first 4 do not care bits, 4 Command Bits + 4 Address Bits which are set by the 8 switches, data_0 for the output and 8 do not care bits. As I understood correctly, the 0 bit should be '1', because of the Internal REF register. But it does not work. Please, if it is possible, could you help me to find the problem? entity pmodda4_test is port( sysclk : in std_logic; -- 100MHz clock ja : inout std_logic_vector(7 downto 0); sw : in std_logic_vector(7 downto 0); ); end pmodad1_test; architecture Behavioral of pmodda4_test is signal data_0 : std_logic_vector(11 downto 0) := (others=>'0'); signal count: STD_LOGIC_VECTOR(27 downto 0) := X"0000000"; signal count2: STD_LOGIC_VECTOR(11 downto 0) := X"001"; signal word_count: STD_LOGIC_VECTOR(5 downto 0) := "000000"; signal sclk0 : STD_LOGIC; signal pout : STD_LOGIC; signal sync0 : STD_LOGIC := '0'; -- signal data: STD_LOGIC_VECTOR(11 downto 0) := X"000"; signal pdata: STD_LOGIC_VECTOR(31 downto 0) := X"00000000"; begin counterp: process(sysclk) begin if rising_edge(sysclk) then count <= count + 1; end if; end process counterp; sclkp: process(sysclk, count) begin elsif rising_edge(sysclk) then if btnl = '1' then -- Use the same freq for both LEDs and sync sclk0 <= count(25); -- Divide 100 MHz / 2^25 => "human" freq else sclk0 <= count(5); -- Divide 100 MHz / 32 = 3.125 MHz end if; end if; end process sclkp; -- Word bits counter: 40 = 32 bits sync + 8 void bits word_countp: process(sclk0) begin if rising_edge(sclk0) then if word_count = "101000" then word_count <= "000000"; else word_count <= word_count + 1; end if; end if; end process word_countp; -- Sync signal signal_syncp: process(sclk0, word_count) begin if rising_edge(sclk0) then if word_count = "000000" then sync0 <= '0'; elsif word_count = "100000" then sync0 <= '1'; end if; end if; end process signal_syncp; signal_shiftp: process(sclk0, word_count, sw, count2) begin if rising_edge(sclk0) then if word_count = "101000" then pdata <= "0000" & sw(7) & sw(6) & sw(5) & sw(4) & sw(3) & sw(2) & sw(1) & sw(0) & data_0 & "00000000"; else pdata <= pdata(30 downto 0) & pdata(31); end if; end if; end process signal_shiftp; -- Data transmission process spip: process(sclk0, word_count) begin if rising_edge(sclk0) then -- Send the signal if sync0 = '0' then pout <= pdata(31); else pout <= '0'; end if; end if; end process spip; ja(0) <= sync0; -- SYNC ja(1) <= pout; -- DOUT ja(2) <= pout; -- Just duplicate DOUT ja(3) <= sclk0; -- SCLK
  6. Hello, dear collegues! I work with Nexys Video board. I use VHDL. Now I try to create project with PmodDA4. I have 4 variables which I obtained inside the project and I want to obtain it like 4 analog signals. I have found an example, but when I tried to implement it for my board it does not work (code is bellow)... If it is some example code for this PmodDA4, please send it... I could not find it for this board. -- The four left-most switches (SW15-SW12) define the command, i.e. 0011 -- The four switches after (SW11-SW8) define the address, i.e. 1111 -- The right-most switch (SW0) defines the regime: working, fast (0) or "human", slow (1) library IEEE; use IEEE.STD_LOGIC_1164.all; use IEEE.STD_LOGIC_unsigned.all; entity pgnd is port( btnc : in STD_LOGIC; sysclk : in STD_LOGIC; sw : in STD_LOGIC_VECTOR(7 downto 0); led : out STD_LOGIC_VECTOR(3 downto 0); jb : out STD_LOGIC_VECTOR(3 downto 0) ); end pgnd; architecture pgnd of pgnd is signal count: STD_LOGIC_VECTOR(27 downto 0) := X"0000000"; signal count2: STD_LOGIC_VECTOR(11 downto 0) := X"001"; signal word_count: STD_LOGIC_VECTOR(5 downto 0) := "000000"; signal sclk0, pout: STD_LOGIC; signal sync0 : STD_LOGIC := '0'; -- signal data: STD_LOGIC_VECTOR(11 downto 0) := X"000"; signal pdata: STD_LOGIC_VECTOR(31 downto 0) := X"00000000"; begin counterp: process(sysclk, btnc) begin if btnc = '1' then count <= X"0000000"; elsif rising_edge(sysclk) then count <= count + 1; end if; end process; sclkp: process(sysclk, count, btnc) begin if btnc = '1' then sclk0 <= '0'; elsif rising_edge(sysclk) then if sw(0) = '1' then -- Use the same freq for both LEDs and sync sclk0 <= count(25); -- Divide 100 MHz / 2^25 => "human" freq else sclk0 <= count(5); -- Divide 100 MHz / 32 = 3.125 MHz end if; end if; end process; -- Word bits counter: 40 = 32 bits sync + 8 void bits word_countp: process(sclk0, btnc) begin if btnc = '1' then word_count <= "101000"; -- # 40 elsif rising_edge(sclk0) then if word_count = "101000" then word_count <= "000000"; else word_count <= word_count + 1; end if; end if; end process; -- Sync signal signal_syncp: process(sclk0, word_count, btnc) begin if btnc = '1' then sync0 <= '1'; elsif rising_edge(sclk0) then if word_count = "000000" then sync0 <= '0'; elsif word_count = "100000" then sync0 <= '1'; end if; end if; end process; signal_shiftp: process(sclk0, word_count, sw, count2, btnc) begin if btnc = '1' then pdata <= X"0" & sw(7 downto 0) & count2 & X"00"; elsif rising_edge(sclk0) then if word_count = "101000" then pdata <= X"0" & sw(7 downto 0) & count2 & X"00"; else pdata <= pdata(30 downto 0) & pdata(31); end if; end if; end process; -- Sawtooth data modulation data_countp: process(sclk0, word_count, btnc) begin if btnc = '1' then count2 <= X"001"; elsif rising_edge(sclk0) and word_count = "101000" then count2 <= count2 + 1; end if; end process; -- Data transmission process spip: process(sclk0, word_count, btnc) begin if btnc = '1' then pout <= '0'; elsif rising_edge(sclk0) then -- Send the signal pout <= pdata(31); end if; end process; JB(0) <= sync0; -- SYNC JB(1) <= pout; -- DOUT JB(2) <= pout; -- Just duplicate DOUT JB(3) <= sclk0; -- SCLK led(0) <= sclk0 when sw(0) = '1' else -- show the real SCLK count(24); -- or indicate device is working on higher freq led(1) <= sclk0 when sw(0) = '1' else not count(24); -- Couple the other leds only if the frequency is "human" led(2) <= pout when sw(0) = '1' else '0'; -- DOUT led(3) <= sync0 when sw(0) = '1' else '0'; -- SYNC end pgnd;
  7. Dear Collegues! I tried to find an answer for my question but I've found nothing... I try to create program in the VHDL. I use PmodAD1, I did Sysclk (16 kHz), Cs (1kHz) signals. I se on the oscilloscope all signalls (Sysclk, Cs and D0). The question is: how to obtain std_logic_vector variable and the integer value of the obtained variable? If it was described, please, give me a link... Code is bellow. library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity pmod_ad1 is Port ( sysclk : in STD_LOGIC; ja : inout STD_LOGIC_VECTOR(7 downto 0); led : out STD_LOGIC_VECTOR(7 downto 0) ); end pmod_ad1; architecture Behavioral of pmod_ad1 is signal CLK_PSC : STD_LOGIC_VECTOR(12 downto 0); signal CS_PSC : STD_LOGIC_VECTOR(5 downto 0); signal PSC : STD_LOGIC_VECTOR(15 downto 0); signal data1_sr : STD_LOGIC_VECTOR(15 downto 0) := (others => '0'); signal temp1 : integer; signal temp2 : integer; signal m : integer :=data1_sr'high-1; signal l : STD_LOGIC_VECTOR(7 downto 0) := (others => '0'); signal r_counter_data : STD_LOGIC_VECTOR(3 downto 0); signal check : STD_LOGIC; signal clk : STD_LOGIC := '0'; signal cs : STD_LOGIC := '0'; begin process(sysclk) begin if rising_edge(sysclk) then if CLK_PSC < "110000110100" then CLK_PSC <= CLK_PSC + 1; else CLK_PSC <= (others => '0'); clk <= not clk; end if; end if; end process; process(clk) begin if rising_edge(clk) then if CS_PSC < "1111" then CS_PSC <= CS_PSC + 1; cs <= '0'; else CS_PSC <= (others => '0'); cs <= '1'; --temp1 <= to_integer(unsigned(data1_sr)); --temp2 <= temp1 / 20; --l <= std_logic_vector(to_unsigned(temp2, l'length)); end if; end if; end process; process(sysclk) begin if rising_edge(sysclk) then if PSC < "1001110001000" then PSC <= PSC + 1; else PSC <= (others => '0'); end if; end if; end process; led <= l; ja(4) <= cs; ja(7) <= clk; ja(0)<=ja(4); ja(1)<=ja(5); ja(3)<=ja(7); end Behavioral;