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  1. Hello, @[email protected]! Thank you VERY MUCH!!!!!! Problem with terrible signal is solved!!!!!(code is bellow) but Some times I have a problem with PmodDA4, I have to switch my sw (Comand bits), then it works normal... It is not very big problemfor me now, but it is better to solve it (in my opinion) word_countp: process(sclk0) begin if rising_edge(sysclk) then if word_count < "10011100001111" then word_count <= word_count + 1; else word_count <=(others => '0'); end if; if word_count < "11111001111" then sy
  2. The problem which I found is: I always send pdata <= "0000" & "0000" & "0000" & DAC_1 & "00000001"; where DAC_1 is std_logic_vector(11 downto 0), I see analog signal from A chanel (Ground - GND, Positive - A) on the digital oscilloscope, but I see terrible result. But if I connect the second oscilloscope channel to the sclk - wave is really good. Some times DAC does not work, so I have to send pdata <= "0000" & "0100" & "0000" & DAC_1 & "00000001", then toutch by the second oscilloscope channel positive wire SYNC then
  3. It works. Code is bellow. I obtain only one analog signal (between GND and Pin A). If somebody find some mistakes, please write about it! Problem was: all things had to be at falling_edge of the sclk0. library ieee; use ieee.std_logic_1164.ALL; use ieee.std_logic_unsigned.ALL; use ieee.numeric_std.all; entity pmodad1_test is port( sysclk : in std_logic; -- 100MHz clock ja : inout std_logic_vector(7 downto 0); sw : in std_logic_vector(7 downto 0); ); end pmodad1_test; a
  4. Dear Dan! Thank you for your quick answer! I can not send you a picture from the simulator, because it sends me some errors, so I cant "switch it on". But I work with oscilloscope, so you can see all signalls what I send to the PmodDA4. 1 - data_0 <= (others =>'1'), 4 Command Bits + 4 Address Bits are '0', and the last one is pout (0) <= '1'.
  5. Dear collegues! Thank you for your answers! I have found an example and rewrited it just a little bit (saw info from http://www.analog.com/media/en/technical-documentation/data-sheets/AD5628_5648_5668.pdf) , page 24. But it does not work...I do not obtain analog signals on the output of the pmodda4. pdata - is data for the output, it consists of: "0000" - first 4 do not care bits, 4 Command Bits + 4 Address Bits which are set by the 8 switches, data_0 for the output and 8 do not care bits. As I understood correctly, the 0 bit should be '1', because of the In
  6. Hello, dear collegues! I work with Nexys Video board. I use VHDL. Now I try to create project with PmodDA4. I have 4 variables which I obtained inside the project and I want to obtain it like 4 analog signals. I have found an example, but when I tried to implement it for my board it does not work (code is bellow)... If it is some example code for this PmodDA4, please send it... I could not find it for this board. -- The four left-most switches (SW15-SW12) define the command, i.e. 0011 -- The four switches after (SW11-SW8) define the address, i.e. 1111
  7. Dear Collegues! I tried to find an answer for my question but I've found nothing... I try to create program in the VHDL. I use PmodAD1, I did Sysclk (16 kHz), Cs (1kHz) signals. I se on the oscilloscope all signalls (Sysclk, Cs and D0). The question is: how to obtain std_logic_vector variable and the integer value of the obtained variable? If it was described, please, give me a link... Code is bellow. library IEEE; use IEEE.STD_LOGIC_1164.ALL; --use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; use IEEE.NUMERIC_STD.ALL; entity