[Need help on QDRII+ implementation]

Hi everyone,

I'm trying to interface with QDRII+ and I use NetFPGA-1G CML Kintex-7

I have done the simulation, it works just fine, however when I implement to the real board, the calibration is failed.

I have 2 questions:

1. Do I need to use exact frequency for sys_clk_p/n (it requires 450.045 MHz)?
2. In the NetFPGA board, I just see 1 pair system_clk_p/n (200MHz), I'm supposed to use it as clk_ref_p/n, what should I use for sys_clk_p/n(450.045MHz)

Thanks in advance.