rangaraj

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  1. Dear Dan & Hamster, Thank you for the reply. Thanks for sharing the application note & code.I understood from the application note we can derive 2pow6 different clocks( HIGH TIME & LOW TIME). In my case, I need something like frequencies 51Mhz,50Mhz,49Mhz........1Mhz. The user will configure any of the frequencies dynamically. Meaning I will get even & odd frequencies. I saw the implementation like this http://ecad.tu-sofia.bg/et/2014/ET2014/AJE_2014/104-I_Pandiev1.pdf All the clock period must have 0.5 duty cycle. i am unable to get all the clock frequencies with any of the implementation. does we have any generic clock generator using MMCM or board clock (100 MHz) ? kindly advise. Note: I only know VHDL coding & i am not familiar with Verilog. Thanks and Regards Lakshman.
  2. dear Hamster, I went through the guide. But I didn't get any clue how to change it. I knew that we need to change the M & F to get the desired frequency as below. CLKFBOUT_MULT_F => 10.500, CLKOUT0_DIVIDE_F => 8.750, I knew counter based solution where we fixed one clock & further divide the clock to get the desired clock. I am looking for something like DCM http://hamsterworks.co.nz/mediawiki/index.php/FreqSwitch is it possible ? Thanks and Regards Lakshman.
  3. Hi, I need to create a clock dynamically from few kilo hertz to 75megaHz. I understood that I can use MMCM. 1.is it possible to dynamically change the MMCM.? 2.Will it work in few 10's of KHz ? Below is 52MHz clock. I want to change dynamically from KHz to Mhz with the below code . -- Clocking PRIMITIVE -------------------------------------- -- Instantiation of the MMCM PRIMITIVE -- * Unused inputs are tied off -- * Unused outputs are labeled unused mmcm_adv_inst : MMCME2_ADV generic map (BANDWIDTH => "OPTIMIZED", CLKOUT4_CASCADE => FALSE, COMPENSATION => "ZHOLD", STARTUP_WAIT => FALSE, DIVCLK_DIVIDE => 1, CLKFBOUT_MULT_F => 10.500, CLKFBOUT_PHASE => 0.000, CLKFBOUT_USE_FINE_PS => FALSE, CLKOUT0_DIVIDE_F => 8.750, CLKOUT0_PHASE => 0.000, CLKOUT0_DUTY_CYCLE => 0.500, CLKOUT0_USE_FINE_PS => FALSE, CLKIN1_PERIOD => 10.0, REF_JITTER1 => 0.000) port map -- Output clocks ( CLKFBOUT => clkfbout_clk_wiz_0, CLKFBOUTB => clkfboutb_unused, CLKOUT0 => clk_out1_clk_wiz_0, CLKOUT0B => clkout0b_unused, CLKOUT1 => clkout1_unused, CLKOUT1B => clkout1b_unused, CLKOUT2 => clkout2_unused, CLKOUT2B => clkout2b_unused, CLKOUT3 => clkout3_unused, CLKOUT3B => clkout3b_unused, CLKOUT4 => clkout4_unused, CLKOUT5 => clkout5_unused, CLKOUT6 => clkout6_unused, -- Input clock control CLKFBIN => clkfbout_buf_clk_wiz_0, CLKIN1 => clk_in1_clk_wiz_0, CLKIN2 => '0', -- Tied to always select the primary input clock CLKINSEL => '1', -- Ports for dynamic reconfiguration DADDR => (others => '0'), DCLK => '0', DEN => '0', DI => (others => '0'), DO => do_unused, DRDY => drdy_unused, DWE => '0', -- Ports for dynamic phase shift PSCLK => '0', PSEN => '0', PSINCDEC => '0', PSDONE => psdone_unused, -- Other control and status signals LOCKED => locked_int, CLKINSTOPPED => clkinstopped_unused, CLKFBSTOPPED => clkfbstopped_unused, PWRDWN => '0', RST => '0'); -- Output buffering ------------------------------------- clkf_buf : BUFG port map (O => clkfbout_buf_clk_wiz_0, I => clkfbout_clk_wiz_0); clkout1_buf : BUFG port map (O => clk_out1, I => clk_out1_clk_wiz_0); Thanks and Regards Lakshman.
  4. Thank you Dan. Thanks and Regards Lakshman.
  5. Dear Dan & Bianca, Thanks for showing the place in schematic. I see that LED , SwBttons & VGA are connected to the same bank. If I change the voltage to 1.8v for bank 14 ,then the other LEDs, VGA's will work ?? Having second thought to use the level shifter as suggested by dan, is that level shifter is bidirectional ? http://store.digilentinc.com/pmod-lvlshft-logic-level-shifter/ kindly advise. Thanks and Regards Lakshman.
  6. Dear Dan, Thank you for the prompt reply. I understood that we need to change the Voltage in the Bank from the link https://www.xilinx.com/support/answers/57045.html . But even I change in the constraint file still we need to change it in the Basys3 board. From your reply I understood that we need to desolder it & solder it to appropriate wire. I went through the schematic I didn't find any 1.8v but we have 2.5v , 3.3v & 1.5v. So I need to give external voltage of 1.8V ? if so which wire I need to desolder in bank 14 or bank 15. will you please point it to me ? Regarding the level shifter, if I am not wrong its a bidirectional levelshitfer (1.8v to 3.3v & 3.3v to 1.8v) am I right ? kindly advise. Thanks and Regards Lakshman.
  7. Hi, recently I bought basys3 board from diligent. In my project I need to use 3 GPIO's both input & Output at 1.8V.Kindly suggest me what I need to change? As from the website , I know I need to change in the constraint file(XDC).bank 14 pins & set CFGBVS = GND. https://www.xilinx.com/support/answers/57045.html do I need to change anything in the board.