danmcb

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Posts posted by danmcb

  1. Well, I'm using the lockdown to do some playng around with the CMOD A7 board that I bought a while back.

    After some fighting with Vivado/Vitis I did manage to setup and build the OOB project. However on a terminal I noticed that the microblaze always seems to die on the memory test.

    I also saw a lot of flaky behaviour of the debug/terminal connetion. I have to restart Vitis many times and so on.

    Eventually I realised the issue ... the memory test seems to be stamping on ts own code area!

    Here is output of the running app:

    --Starting Memory Test Application--
    NOTE: This application runs with D-Cache disabled.As a result, cacheline requests will not be generated
    Testing memory region: Cellular Ram
        Memory Controller: emc
             Base Address: 0x60000000
                     Size: 0x0007ffff bytes

    but here is the output of the downloader:

    Downloading Program -- /home/daniel/work/vivado/Cmod_OOB/vitis/Debug/CMOD_OOB.elf
        section, .vectors.reset: 0x00000000 - 0x00000007
        section, .vectors.sw_exception: 0x00000008 - 0x0000000f
        section, .vectors.interrupt: 0x00000010 - 0x00000017
        section, .vectors.hw_exception: 0x00000020 - 0x00000027
        section, .text: 0x60000000 - 0x600032ff
        section, .init: 0x60003300 - 0x6000333b
        section, .fini: 0x6000333c - 0x6000335b
        section, .ctors: 0x6000335c - 0x60003363
        section, .dtors: 0x60003364 - 0x6000336b
        section, .rodata: 0x6000336c - 0x60003a0b
        section, .sdata2: 0x60003a0c - 0x60003a0f
        section, .data: 0x60003a10 - 0x60003d33
        section, .sdata: 0x60003d34 - 0x60003d37
        section, .sbss: 0x60003d38 - 0x60003d37
        section, .bss: 0x60003d38 - 0x60003e47
        section, .heap: 0x60003e48 - 0x60004647
        section, .stack: 0x60004648 - 0x60004a47

    How is this supposed to work? is there something strange with my project? perhaps the microblaze is meant to be running out of some other RAM block? is there some liner config in Vitis that I missed?

    (EDIT :

    after some more prodding about, I found that indeed I seem to have the wrong linker script lscript.ld - there was another one which uses local memory instead of the external RAM.

    but when I replace it, Vitis complains that the hardware info eported by Vivado is not valid. So I guess this was somehow generated by Vivado -but where?)

    thanks!

     

    Daniel

     

     

     

     

  2. well, I haven't programmed using command line. Only withe the MIMAS2 util. Can you see the device with impact? that should work (there is a pdf about using impact with HS3 somewhere on digilent site)

    also you could try running JTAG Loader debian version just to see if it finds your HS3

    that all might tell you if it is a driver/version issue or something with your programming file?

     

  3. no, I have only programmed with JTAG loader or the windows app provided by Numato.

     

    Do you have the latest cse drivers? I noticed that the ones in the Xilinx distro were older - this is what I now have:

     

    [email protected]:~$ cat .cse/lin64/14.1/plugins/Digilent/libCseDigilent/libCseDigilent.xml
    <?xml version="1.0" encoding="UTF-8" ?>
    <!-- Copyright (c) 2007 Xilinx, Inc.  All rights reserved. -->
    <CsePlugin>
        <fullname>Digilent Plug-in</fullname>
        <libname>libCseDigilent</libname>
        <vendor>Digilent</vendor>
        <version>2.5.2</version>
    .
      .
      .
      (etc)

    I don't know if that helped but I did update them.

     

  4. hi Billy - I have it working. Indeed, Adept runtime and utilities were the issue. I not have JTAG Loader (debian) and Impact working fine. (This is on Debian buster - testing )

    process is explained here for anyone that needs it (this is about Zynq, but seems to be fine with my Spartan6 / ISE 14.7 setup).

    One thing to watch out for is that your build script loads the necessary paths - this is mine, for reference:

    #!/bin/bash
    
    # simple build script for the picoblaze assembler
    # compiles the code, and loads it onto target RAM
    # note that to make changes permanent you must then rebuild the .bin file
    # using ISE and burn it onto the target using the MIMAS2 config tool
    # (which is unfortunately windows only)
    
    # make sure we see opbasm and friends
    export PATH="$HOME/.local/bin:$PATH"
    
    # make sure we see shared libs 
    source /opt/Xilinx/14.7/ISE_DS/settings64.sh
    
    # compile the ASM file
    opbasm -i dlh_firmware.psm -6 -s 64 -x -m4 -m 2048
    if [ $? -ne 0 ]; then
    	echo "ASSEMBLY FAILED - aborting."
    else
    	echo "ASSEMBLY OK - copying formatted source to .psm"
    	/bin/mv dlh_firmware.fmt dlh_firmware.psm
    	./JTAG_Loader_Debian_64 -l dlh_firmware.hex
    fi

    (I am using JTAG-HS3 witha  Numato MIMAS2 board, hence comments - should adapt ok for other targets).

     

     

    many thanks!

    Daniel

     

     

  5. I am having similar issues.  I have programmed SPartan 6 with HS3 in Win 7 with some success, but for various reasons (mostly the fact that it is gettng harder to stay with Win7) I decided to set up a Linux dev environement.

    After some fighting, I have ISE14.7 running OK.

     

    But cable drivers is another issue. The HS3 is seen by JTAG Loader but no driver is found:

     

    <code>

    [email protected]:~/work/dlaserhead$ source /opt/Xilinx/14.7/ISE_DS/settings64.sh
    . /opt/Xilinx/14.7/ISE_DS/common/.settings64.sh /opt/Xilinx/14.7/ISE_DS/common
    . /opt/Xilinx/14.7/ISE_DS/EDK/.settings64.sh /opt/Xilinx/14.7/ISE_DS/EDK
    . /opt/Xilinx/14.7/ISE_DS/PlanAhead/.settings64.sh /opt/Xilinx/14.7/ISE_DS/PlanAhead
    . /opt/Xilinx/14.7/ISE_DS/ISE/.settings64.sh /opt/Xilinx/14.7/ISE_DS/ISE
    [email protected]:~/work/dlaserhead$
    [email protected]:~/work/dlaserhead$
    [email protected]:~/work/dlaserhead$ ./JTAG_Loader_Debian_64 - dlh_firmware.hex
       __  _                 __                  _                  
       \ \| |_  __ _  __ _  / /   ___   __ _  __| | ___ _ __      
        \ \ __|/ _` |/ _` |/ /   / _ \ / _` |/ _` |/ _ \ '__|   
     /\_/ / |_| (_| | (_| / /___| (_) | (_| | (_| |  __/ |         
     \___/ \__|\__,_|\__, \____/ \___/ \__,_|\__,_|\___|_|
                     |___/                                          
     JTAG Loader by Kris Chaplin, Xilinx UK  
     Build : Date: Mar 16 2015, Time: 17:01:07              
     Target: Linux 4.19.0-4-amd64 x86_64 #1 SMP Debian 4.19.28-2 (2019-03-15)        
     Use the -h option if you need help      

    Info:============================================
    Info:CABLE name used in scanChain: auto, cableArgCount=0
    Info:============================================
    Info:Connecting to hw_server...
    Info:Attempting to launch hw_server...
    Info:
    ****** Xilinx hw_server v2013.3
      **** Build date : Sep 24 2013-19:37:55
        ** Copyright 1986-1999, 2001-2013 Xilinx, Inc. All Rights Reserved.

    INFO: hw_server application started
    INFO: Use Ctrl-C to exit hw_server application

    INFO: Set the HW_SERVER_ALLOW_PL_ACCESS environment variable to 1 to access any PL address memory in the TCF debugger memory window.

    Info:Connection failed.
    Info:AutoDetecting cable. Please wait.
    Info:*** WARNING ***: When port is set to auto detect mode, cable speed is set to default 6 MHz regardless of explicit arguments supplied for setting the baud rates
    Info:If you are using the Platform Cable USB, please refer to the USB Cable Installation Guide (UG344) to install the libusb package.
    Info:Connecting to cable (Usb Port - USB21).
    Info:Checking cable driver.
    Info: Linux release = 4.19.0-4-amd64.
    Warning:WARNING:Cse -  Module windrvr6 is not loaded. Please reinstall the cable drivers. See Answer Record 22648.
    Info:Cable connection failed.

    </code>

    The cable is found, but there is an issue finding the driver. But in fact, something that looks like one does exist ... :

    [email protected]:~$ ls .cse/lin64/14.1/plugins/Digilent/libCseDigilent/
    libCseDigilent.so  libCseDigilent.xml

     

    but the question is - how do I get JTAG loader t actually see it and use it ... ?

     

    Daniel

     

     

     

     

  6. Hi all,

    I have been using MAX32 in bare-metal mode quite a bit, and I wrote some scheduler code for it. The code also does buffered debug printing over USB, and some basic error handling. I use this as start point for projects where I want very predictable timing. I find MAX32 very useful for this.

    The code is on Github here

    https://github.com/danmcb/MAX32-RT-Scheduler

    and there is a write up at my website here:

    http://www.mcbeeaudio.com/lab//MAX32-real-time-scheduler.html

    This mighty make a nice start point for anyone that has been using MAX32 as an Arduino but wants to get into writing C on it. (Everything builds with the free Microchip tools.)

    all the best

    Daniel

     

     

     

  7. I just received one of these boards and have been able to carry out the most basic tutorials, but the programming interface seems very flaky.

    I note on other forum threads like this:

    https://forum.digilentinc.com/topic/4769-vivado-hardware-manager-disconnects-cmod-a7-target-in-win7/

    that other users have also had issues. There has been some suggestion that USB cables are an issue.

    This is a problem. I previously used a different board with a Spartna FPGA and a Digilent JTAG Hs3, and I was able to program the board very reliably - in a second or two. I was able to put a PicoBlaze on the target with no problems, and update the code very efficiently. However that board is no longer available, so I selected the CMod as a replacement for a project which is quite critical.

    I just don't have time for flaky interfaces, debugging other people's problems, or randomly swapping cables and hoping. Is there any way to program the CMOD with the HS3? Is there any proven resolution for the USB programming problem? 

    thanks

    Daniel

     

     

  8. I'm using Diptrace to lay out a board. I just need the mechanical positiions of holes, connectors and so on. thanks. I don't really want to get involved with Eagle, it isn't hard to create a component in Diptrace. But in fact it is (almost) an Arduino MEGA, I found some drawings for that.

  9. I've done quite some work with this board, and I have a mini-RTOS that I use on it. Am planning to post the source on github sometime, when I do I will let you know.

    basically it isn't that hard, if you know MPLAB - this is what is involved:

    1. set up an MPLABX project with the right chip variant.

    2. set up config registers on the chip to use the correct clock (external xtal oscillator is a good basic option for this board), you could also use the internal RC if you wanted although not much point.

    3. write a very simple C program - I suggest just main() with a silly loop to turn on and off the user LED

    4. compile and load, see if you can get the LED flashing

    If this works, you are off! Next step would probably be to get the UART working so you have debug output. (You can easily do this over USB with this board as it has the hardware on board.)

     

     

  10. Hi - I just received my HS3 adaptor, am learning FPGA on a Numato Mimas dev board. But the Mimas has a 14 pin connector on 0.1" pitch (looks like a standard ribbon connector).

    Checking the schematic against the HS3 docs, the pinout is the same.

    is an adapter available? or can you give the connector type for the HS3 so I can make one?

     

    thanks

     

    Daniel