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  1. @jpeyron thanks for the 3D data, it's just in time for me to integrate multiple boards into a chassis. Can I briefly say the 10GbE fiber interface from the FMC connector works. The IBERT runs over 10 min without logging any error from the fiber channels (SFP+) in the Vivado Serial I/O Links panel. Also I put two SATA connectors for cheap internal connection, those SATA connections also run stable under 10GbE until the SATA cable been touched. So the fiber is a lot more reliable and I'll probably run half of the speed for the SATA based internal connection.
  2. @Biancaan early version of the STEP file would be very useful, as I'm designing a non-standard FMC interface board, I can put them together before getting the real PCB. regards
  3. @jpeyron There is probably no need to bother your mechanical engineer. Try Garrett A, Open the PCB file, from the Altium Designer, File->Export->STEP 3D, the job done. regards
  4. Hi, Jon, I did consider the NetFPA-SUME and have contacted the netfpga team. With the academic discount, as Garrett suggested, the performance to cost ratios of the two boards are quite comparable. However, the idea of my FPGA cluster is to have light nodes, so that at later stage I can install hundreds of them, and each node can have a simple firmware. For example, I'll only need to handle a 32bit DDR interface instead of two 64bit DDR plus QDR as with the NetFPGA SUME board. The question about the DP connection was actually trying to split a DP cable and solder it directly to a SFP+ connector for a quick 10G test. However, since that is not going to be my end solution, I'll skip it for the moment. I'll just route a simple FMC adaptor PCB with a few SFP+ connections to test the 10G performance. BTW, do you think there is chance to get a copy of the 3D shape of the Genesys 2 board? e.g. a STEP file. So that I can integrate it to the CAD system when designing a chassis to hold many of these boards. Regards, David
  5. Another thought. As I was checking the schematics for the GTX to FMC connections, I realized there were also four lanes to each DP connector. Also, since DP 1.3 allows each lane up to 8Gbps, any chance I could just hook a SFP+ transceiver to the DP port and use 1 lane for a 10GbE interface? PS, is the gerber file for the Genesys 2 board available to the public? just want to know the physical space of the two DP connectors, especially when I haven't got the board yet.
  6. @sbobrowicz Thanks for the information. The NetFPGA SUME board is particularly interesting.
  7. Hi, thank you all for the inputs. Let's do not worry too much about the standards. Given the cost for an academic user, I think I'll just buy one and give it a test. If it works at 6Gbps which means there is no vital fault in the board, it has good chance to run at 10Gbps. BTW, anyone knows where to get a decent (in terms of price) FMC to SFP+ adaptor? I searched the internet but the solution I could find is more expensive than the Genesys2 board. I prefer not to build one myself. It does not only take time, also there is risk in new hardware. Regards.
  8. Hi, I'm trying to build an FPGA cluster for vector processing. I'm interested in the Genesys 2 board. According to the specification, it should be able to provide 10GbE access via the FMC interface by, .for example, adding another fibre transceiver board. So that I can run 10GbE for the inter-board communication. However, apart from the theory, has anyone actually succeeded in getting a 10G link from the Genesys 2 FMC connector? or put it another word, has the transceiver channels in the FMC been tested to achieve the 10G performance? Please feel no offence, just there are list of reasons that a 10G link could fail and for many times I saw the high-end specifications came with small footprints to limit its availability. After all I do not want to end up with a pile of boards going no where. Many thanks, David