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  1. Hi @jpeyron, The errors are just messages that some pins (the tmds_in and hdmi_in_ddc) have not been assigned to a package pin, so when I go to synthesize and implement, it auto-assigns pins that are incorrect for that interface.
  2. Hi @jpeyron, I did run the HDMI tutorial, and it worked just fine, but that's because the tutorial uses constraints in the XDC file to place the signals by name, rather than using the "board interfaces" like I am hoping to do. I did follow the tutorial to install the board files, and I know Vivado is reading them since it found the board and the interfaces, it just doesn't place them right. Also, as far as the vivado library, you can just pull from git with git pull --recursive <link> which will also pull the vivado library submodule. The main thing is the demo gets around the IO placements with constraints (which look hand-written rather than autogenerated), which makes me suspect Digilent also couldn't get the board file to be read in 100% correctly. I just had Vivado create the wrapper for me, so I doubt that's the issue (I've attached it here). The IP repo just has the digilent library that I downloaded and set as a default library for all projects, but the project directory itself has the library since I used the --recursive option during git pull. hdmiPass_wrapper.v
  3. I was attempting to use the Board tab within a block design in Vivado 2016.4 to connect some of the board interfaces on a Nexys Video FPGA board. In particular, the HDMI In component goes and instantiates both the TMDS signals in, as well as the DDC signals out, and Vivado marks the HDMI In component as connected. However, when I go to synthesize or elaborate the design, I get a bunch of messages telling me that top-level ports have not been assigned to an IO, and if I open up the I/O Port window, I can see that there's no package pin assigned to the HDMI ports. The only package pins that seem to be assigned are the board clock and reset. I don't think it's a problem with the board files, since I can clearly see from the Board tab that the interfaces are there. And the tool did know which pins were connected to clock and reset. My concern is that it looks like the iostandard and loc properties in part0_pins.xml aren't being understood by Vivado, since the ports ended up unconnected and some have the wrong IO standard (see screenshots). I would upload the project file, but it looks like its too big for the forum by a few MBs, so I posted some screenshots instead, as well as the board files. Does anyone know what could be wrong? I know a UCF file with LOC constraints will work, but that defeats the whole point of the board files that include pin definitions. mig.prj board.xml part0_pins.xml preset.xml