I was attempting to use the Board tab within a block design in Vivado 2016.4 to connect some of the board interfaces on a Nexys Video FPGA board. In particular, the HDMI In component goes and instantiates both the TMDS signals in, as well as the DDC signals out, and Vivado marks the HDMI In component as connected. However, when I go to synthesize or elaborate the design, I get a bunch of messages telling me that top-level ports have not been assigned to an IO, and if I open up the I/O Port window, I can see that there's no package pin assigned to the HDMI ports. The only package pins that seem to be assigned are the board clock and reset.
I don't think it's a problem with the board files, since I can clearly see from the Board tab that the interfaces are there. And the tool did know which pins were connected to clock and reset. My concern is that it looks like the iostandard and loc properties in part0_pins.xml aren't being understood by Vivado, since the ports ended up unconnected and some have the wrong IO standard (see screenshots).
I would upload the project file, but it looks like its too big for the forum by a few MBs, so I posted some screenshots instead, as well as the board files.
Does anyone know what could be wrong? I know a UCF file with LOC constraints will work, but that defeats the whole point of the board files that include pin definitions.