BeamPower

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  1. I'm not sure it's the C-code that's the problem. I think there's a wiring problem on the block diagram. Has anyone had a chance to view the document I attached earlier? Thanks.
  2. How do you paste images into a posting? I copy and paste from OpenOffice, but all the graphics get lost.
  3. Hello, I am running Vivado 2016.4 on a Windows 10 box. I am attempting to learn how to use the OLEDrgb. I restarted the project and got no errors this time. But the display is slow as molasses in January! It blips out one letter every 10 seconds or so. Very odd. Maybe there's a clocking error on my Block Design? Maybe someone can help me? Say, is there some way I could sent you my project file for you to look at? Anyway, I will attached a separate OpenOffice file that includes popups and graphic snapshots. I added 2 clocks as instructed, but there's an unconnected pin down there. The drawing in the tutorial shows a completely different connection. Let me back up to the beginning. First of all, is this an accurate drawing of your basic Microblaze circuit? My drawing looks like this: If I take the simplistic approach, my drawing has 9 blocks including the OLEDrgb interface connector. The tutorial drawing has 11 blocks prior to the addition of the OLEDrgb interface coinnector. Somehow, even with my abbreviated circuit, I have established a connection to the OLEDrgb. The OLEDrgb is just very, very, slow! I notice the final drawing for the tutorial has 14 blocks. Wow! I wish I could read it... Thanks and have a great weekend. Arty OLEDrgb slow.odt
  4. I'm now working with an Arty board. I was able to build a Microblaze example and print Hello World to the console. So now I'm moving forward, slowly, into Pmods. I thought I'd try the OLEDrgb Pmod first. Question: Starting with the Hello World example, how do I clean up the pre-existing C code in order to start with a clean slate? Is it necessary to delete the old code samples, or can I just leave them in the workspace? I saved the project as a new name. A new folder was created in my c:VivadoProjects folder. The example talked about creating the clocks. The clock reconfiguration does not quite match what's on the screen. First of all, there was no 100 MHz option for Clock 0. Aren't we based on a 166.667 MHz clock, so how can that get reduced to 100 MHz exactly? It said to make a clock less than (or equal to) 50 MHz. So I set the following clocks: Clock 0 9947 ps (100.52831 MHz) Clock 1 21276 ps (47 MHz) And I wired them to the Pmod as instructed. I initiated a Generate Bitstream. Some popups appeared. One was a critical warning: [IP_Flow 19-4965] IP PmodOLEDrgb_axi_quad_spi_0_0 was packaged with board value 'digilentinc.com:zybo:part0:1.0'. Current project's board value is 'digilentinc.com:arty:part0:1.1'. Please update the project settings to match the packaged IP. [IP_Flow 19-4965] IP PmodOLEDrgb_axi_gpio_0_1 was packaged with board value 'digilentinc.com:zybo:part0:1.0'. Current project's board value is 'digilentinc.com:arty:part0:1.1'. Please update the project settings to match the packaged IP. [IP_Flow 19-4965] IP PmodOLEDrgb_pmod_bridge_0_0 was packaged with board value 'digilentinc.com:zybo:part0:1.0'. Current project's board value is 'digilentinc.com:arty:part0:1.1'. Please update the project settings to match the packaged IP. No other popups Synthesis is proceeding Implementation is proceeding When I get to the part about copying the source code to the Pmod src folder, I got some errors. It needed the h files and all the xspi files copied up there too. After I copied up all the needed files from the system wrapper, the C code is crashing on this error: 'XPAR_PMODOLEDRGB_0_AXI_LITE_GPIO_BASEADDR' undeclared (first use in this function) I don't think I can move forward until this is resolved. Here's a snippet of the code that's found in main.c void DemoInitialize() { OLEDrgb_begin(&oledrgb, XPAR_PMODOLEDRGB_0_AXI_LITE_GPIO_BASEADDR, XPAR_PMODOLEDRGB_0_AXI_LITE_SPI_BASEADDR); } How do I fix this?
  5. Cmod A7 Programming Guide Tutorial Errors.odt Hello, I tried to run the tutorial for Cmod A7 Programming, but ran into some errors. https://reference.digilentinc.com/learn/programmable-logic/tutorials/cmod-a7-programming-guide/start How many ways are there to program the Cmod A7? Right at the top of the tutorial it says there are 2 ways to program the Cmod A7. Then one paragraph later it says 3 ways. Then in section 2 it says 4 ways. It keeps growing. There are two ways you can program the Cmod A7: JTAG Quad SPI Flash This tutorial will walk you through what you need to know to get started on your projects and program your Cmod A7 FPGA board using each of the three possible methods. It is recommended that you first complete the “Getting Started with Vivado” guide before continuing with this project. 2. Creating Program File For the four ways to program your Cmod A7 FPGA... Can we work on a little consistency here? Then in the hardware prerequisites is an odd little item. Hardware Prerequisites Cmod A7 FPGA board Micro-USB cable Micro SD card What provisions are there for a Micro SD card on the Cmod A7? Section 1.4 starts with an error. 1.4) In this window, you can select any source files or directories that you'll want to use in your projects. We can also select which language we'll be programming in. For this project just keep the default settings. Create a new file by clicking the Create File button. Did you mean to click on Add Files instead? 2.1) In order to program the FPGA on startup we have to specify that we want to generate a .bin file. This can be done by clicking Tools> Project Settings> Bitstream. In this window we will check the box next to .bin_file. Now Vivado will create both a .bit, and .bin file when we generate a Bitstream. You need to add Click on OK to dismiss the project settings. Upon clicking view Synthesized Design, I got an error: Vivado 2016.4 has an added selection Also, not sure if this is a feature new to Vivado 2016.4, but the constraints need to be updated either in a new file or the existing file. I selected the existing file. I clicked on Generate Bitsteam. I got an error. Bitstream Generation Failed Implementation Write Bitstream [DRC 23-20] Rule violation (NSTD-1) Unspecified I/O Standard - 1 out of 4 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned specific value. This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all I/O standards. This design will fail to generate a bitstream unless all logical ports have a user specified I/O standard value defined. To allow bitstream creation with unspecified I/O standard values (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks NSTD-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: led[0]. [Vivado 12-1345] Error(s) found during DRC. Bitgen not run. Okay. How to proceed? A OpenOffice text file is attached that includes image captures of pop-up errors and a complete listing of the Log file. Thank you.
  6. This path is 709 characters long! C:/Xilinx/Vivado/2016.4/bin;C:/Xilinx/Vivado/2016.4/lib/win64.o;C:/Xilinx/Vivado/2016.4/tps/win64/jre/bin/server;C:/Xilinx/Vivado/2016.4/tps/win64/jre/bin;C:/Xilinx/SDK/2016.4/bin;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado_HLS/2016.4/bin;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\WINDOWS\system32;C:\WINDOWS;C:\WINDOWS\System32\Wbem;C:\WINDOWS\System32\WindowsPowerShell\v1.0\;C:\Python\WinPython-64bit-2.7.12.2Zero\python-2.7.12.amd64;C:\Program Files\MATLAB\R2016b\bin;C:\Program Files\Microsoft SQL Server\130\Tools\Binn\;C:\Program Files\doxygen\bin;C:\Users\User\AppData\Local\Microsoft\WindowsApps;C:\Program Files\CMake\bin Is this path local to Xilinx? Or is it the Windows path? I am running Windows 10. In the Windows API (with some exceptions discussed in the following paragraphs), the maximum length for a path is MAX_PATH, which is defined as 260 characters. A local path is structured in the following order: drive letter, colon, backslash, name components separated by backslashes, and a terminating null character. MATLAB is installed on this PC. I remember when installing MATLAB, the 260 character limit was removed. I have also read there are ways to hack the registry to remove the 260 character limit.
  7. Hello Dan, I typed in which mb-gcc on the Tcl command line and got this result. Does this mean I have no mb-gcc? Or at least no path to mb-gcc? I will check for it's existence anywhere on the PC. which mb-gcc WARNING: [Common 17-259] Unknown Tcl command 'which mb-gcc' sending command to the OS shell for execution. It is recommended to use 'exec' to send the command to the OS shell. C:\WinAVR-20100110\utils\bin\which.EXE: no mb-gcc in (C:/Xilinx/Vivado/2016.4/bin;C:/Xilinx/Vivado/2016.4/lib/win64.o;C:/Xilinx/Vivado/2016.4/tps/win64/jre/bin/server;C:/Xilinx/Vivado/2016.4/tps/win64/jre/bin;C:/Xilinx/SDK/2016.4/bin;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/bin/nt64;C:/Xilinx/Vivado/2016.4/ids_lite/ISE/lib/nt64;C:/Xilinx/Vivado_HLS/2016.4/bin;C:\WinAVR-20100110\bin;C:\WinAVR-20100110\utils\bin;C:\WINDOWS\system32;C:\WINDOWS;C:\WINDOWS\System32\Wbem;C:\WINDOWS\System32\WindowsPowerShell\v1.0\;C:\Python\WinPython-64bit-2.7.12.2Zero\python-2.7.12.amd64;C:\Program Files\MATLAB\R2016b\bin;C:\Program Files\Microsoft SQL Server\130\Tools\Binn\;C:\Program Files\doxygen\bin;C:\Users\User\AppData\Local\Microsoft\WindowsApps;C:\Program Files\CMake\bin) I found several instances of mb-gcc on the drive. The one closest to Vivado 2016.4 is here: C:\Xilinx\SDK\2016.4\gnu\microblaze\nt\bin How do I correct the path to get me there?
  8. Hello, Does Digilent have some guidelines on how to operate a PmodMIC3 with a CMOD A7 board? First of all, is the CMOD A7 a good host platform for the PmodMIC3? Or is the ARTY a better choice? Is it possible to record sound, digitize it on the FPGA at 44.1 kHz, then send it to the PC via the USB port? I looked all over the Digilent site and GitHub, but found nothing. Thanks.
  9. Uh oh... I might have my projects mixed up. But I tried moving forward. The UART seems to show signs of life. When I reprogram the board, I get some text on the COM6 serial port terminal (TeraTerm). CMOD A7 GPIO/UART DEMO! Also button presses were detected. CMOD A7 GPIO/UART DEMO! Button press detected! Button press detected! Button press detected! Button press detected! I don't understand the next few steps. Didn't I already program the FPGA in step 3 above? 4. Export to SDK I tried to export to SDK, but I got an error. Cannot Export Hardware The hardware handoff file (.sysdef) does not exist. It may not have been generated due to: 1. A bitstream might not have been generated. Generate Bitstream and export again, or do not request a bitstream to be included in export. 2. There are no block design hardware handoff files. Check the vivado log messages for more details. So I tried to generate the bitstream again. But it seems to run on and on. Vivado Commands Synthesis Implementation Design Initialization [filemgmt 56-147] Overwrite of existing file isn't enabled. Please specify -force to overwrite file [C:/VivadoProjects/Cmod-A7-35T-GPIO-master/proj/GPIO.runs/impl_1/.Xil/Vivado-5392-DESKTOP-7CSAO6T/clk_wiz_0/clk_wiz_0.dcp] [Vivado 12-2489] -input_jitter contains time 0.833330 which will be rounded to 0.833 to ensure it is an integer multiple of 1 picosecond ["c:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/ip/clk_wiz_0/clk_wiz_0.xdc":57] Where do I enter the -force command? I tried to enter it on the Bitstream settings tab, but that did not help. 5. Import the SDK files 6. Program the FPGA 4. Run the Project (should this be step 7?) Maybe best to start over from square 1.
  10. Thanks AndrewHolzer. I tried that upgrade on the Out of Box Demo and it seemed to work there. I'll have to try it with this GPIO Demo project. You would think Digilent would review their tutorials? How many people get frustrated with this stuff and quit? Thanks again.
  11. Now what? There was a forum entry in March from jpeyron about an out of date clock wizard. Instead of deleting and recreating the clock wizard, I saw an option to update it. So I ran an update on the IP for clk_wiz_0 I also converted to core container format. upgrade_ip -vlnv xilinx.com:ip:clk_wiz:5.3 [get_ips clk_wiz_0] -log ip_upgrade.log Upgrading 'clk_wiz_0' INFO: [IP_Flow 19-3422] Upgraded clk_wiz_0 (Clocking Wizard 5.3) from revision 1 to revision 3 INFO: [IP_Flow 19-1686] Generating 'Instantiation Template' target for IP 'clk_wiz_0'... INFO: [Coretcl 2-1525] Wrote upgrade log to 'C:/VivadoProjects/Cmod-A7-35T-GPIO-master/proj/ip_upgrade.log'. export_ip_user_files -of_objects [get_ips clk_wiz_0] -no_script -sync -force -quiet convert_ips [get_files C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/ip/clk_wiz_0/clk_wiz_0.xci] INFO: [filemgmt 56-106] Converting IP 'clk_wiz_0' into core container format. INFO: [filemgmt 56-101] Creating core container 'C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/ip/clk_wiz_0.xcix' for IP 'clk_wiz_0' export_ip_user_files -of_objects [get_files C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/ip/clk_wiz_0/clk_wiz_0.xci] -sync -lib_map_path -force -quiet set_property coreContainer.enable 1 [current_project] 2. Build the Project I then executed generate Bitstream Bitstream generation successful Synthesis completed with 51 warnings. Implementation completed with 3 warnings DRC violations 1 warning No errors 3. Program the Board Hardware target was selected Multi-color LED is working. Success?
  12. Cmod A7 Out of Box Demo errors I have the CMPD A7 with the 35T chip, so I downloaded from GITHub the project repository named: Cmod A7 35T Project Repository 1.2) Generate the User project in the Projects folder by following this guide before continuing: How to Generate a Project from Digilent's Github What is the User project? Did you mean create_project.tcl? I ran Vivado 2016.4 and started with a clean slate. On the Tcl command line I changed directory to the Cmod A7 35T Project Repository cd C:/VivadoProjects/Cmod-A7-35T-GPIO-master/proj/ I then ran the tcl file source ./create_project.tcl A new project was created. Generate Bitstream a warning showed up immediately WARNING: [Runs 36-337] The following IPs are either missing output products or output products are not up-to-date for Implementation target. Since these IPs are locked, no update to the output products can be done. Please select 'Report IP Status' from the 'Tools/Report' menu or run Tcl command 'report_ip_status' for more information. C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/ip/clk_wiz_0/clk_wiz_0.xci Implementation Design Initialization [Project 1-486] Could not resolve non-primitive black box cell 'clk_wiz_0' instantiated as 'inst_clk' ["C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/hdl/GPIO.vhd":267] Opt Design [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'inst_clk' of type 'inst_clk/clk_wiz_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run. I ran the Tcl command report_ip_status report_ip_status Copyright 1986-2016 Xilinx, Inc. All Rights Reserved. ------------------------------------------------------------------------------------ | Tool Version : Vivado v.2016.4 (win64) Build 1733598 Wed Dec 14 22:35:39 MST 2016 | Date : Fri Apr 28 14:32:28 2017 | Host : DESKTOP-7CSAO6T running 64-bit major release (build 9200) | Command : report_ip_status ------------------------------------------------------------------------------------ IP Status Summary 1. Project IP Status -------------------- Your project uses 1 IP. Some of these IP may have undergone changes in this release of the software. Please review the recommended actions. More information on the Xilinx versioning policy is available at www.xilinx.com. Project IP Instances +---------------+-----------------------------------------------------+----------------+-----------+--------------------+---------+--------------+------------+----------------------+ | Instance Name | Status | Recommendation | Change | IP Name | IP | New Version | New | Original Part | | | | | Log | | Version | | License | | +---------------+-----------------------------------------------------+----------------+-----------+--------------------+---------+--------------+------------+----------------------+ | clk_wiz_0 | IP revision change. IP board change. IP part change | Upgrade IP | *(1) | Clocking Wizard | 5.3 | 5.3 (Rev. 3) | Included | xc7a15tcpg236-1 | | | | | | | (Rev. | | | | | | | | | | 1) | | | | +---------------+-----------------------------------------------------+----------------+-----------+--------------------+---------+--------------+------------+----------------------+ *(1) c:/Xilinx/Vivado/2016.4/data/ip/xilinx/clk_wiz_v5_3/doc/clk_wiz_v5_3_changelog.txt Now what?
  13. Thanks Dan, I'll give that a try tomorrow on my work laptop. I went to my desktop PC at home and got good results. Interesting to see there are three builds in that make file. On my work laptop, the first build was unable to start, . 22:37:39 **** Build of configuration Debug for project HelloWorld **** make all 'Building file: ../src/helloworld.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../HelloWorld_bsp/microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c" 'Finished building: ../src/helloworld.c' ' ' 'Building file: ../src/platform.c' 'Invoking: MicroBlaze gcc compiler' mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/platform.o" -I../../HelloWorld_bsp/microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -MMD -MP -MF"src/platform.d" -MT"src/platform.o" -o "src/platform.o" "../src/platform.c" 'Finished building: ../src/platform.c' ' ' 'Building target: HelloWorld.elf' 'Invoking: MicroBlaze gcc linker' mb-gcc -Wl,-T -Wl,../src/lscript.ld -L../../HelloWorld_bsp/microblaze_0/lib -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -o "HelloWorld.elf" ./src/helloworld.o ./src/platform.o -Wl,--start-group,-lxil,-lgcc,-lc,--end-group 'Finished building target: HelloWorld.elf' ' ' 'Invoking: MicroBlaze Print Size' mb-size HelloWorld.elf |tee "HelloWorld.elf.size" text data bss dec hex filename 2916 292 3128 6336 18c0 HelloWorld.elf 'Finished building: HelloWorld.elf.size' ' ' 22:37:41 Build Finished (took 2s.286ms) I see a very subtle difference between the two. The one that failed had two extra settings: -ffunction-sections -fdata-sections Would that make any difference?
  14. Hello Digilent, I went to a different PC and was able to slug my way through the first tutorial: Cmod A7 - Getting Started with Microblaze I got some output on the TeraTerm terminal which was mildly satisfying. Next I stepped into the second tutorial. Cmod A7 GPIO Demo First of all, it isn’t clear if you’re supposed to leave Vivado with the project from Tutorial 1 still loaded? Or close down Vivado and start with a fresh GUI? Anyway, I tried both ways. Neither seems to work. I have attached a detailed record of what I did, but for some reason I’m getting some errors and can’t move forward. At my new location, I’m using Vivado 2016.4 and all the requisite software. I'm following the tutorial step-by-step. I'm getting implementation errors. A summary of errors is as follows: Implementation (2 errors, 1 critical warning) Design Initialization (1 CRITICAL WARNING) [Project 1-486] Could not resolve non-primitive black box cell 'clk_wiz_0' instantiated as 'inst_clk' ["C:/VivadoProjects/Cmod-A7-35T-GPIO-master/src/hdl/GPIO.vhd":267] Opt Design (2 ERRORS) [DRC 23-20] Rule violation (INBB-3) Black Box Instances - Cell 'inst_clk' of type 'inst_clk/clk_wiz_0' has undefined contents and is considered a black box. The contents of this cell must be defined for opt_design to complete successfully. [Vivado_Tcl 4-78] Error(s) found during DRC. Opt_design not run. Is this salvageable? A detailed listing is in the attachment. 20170427 notes tutorial 2 detailed.docx
  15. Being a sucker for shiny, new products, I installed Vivado 2017.1 which includes SDK 2017.1 Does this count for making sure gcc was installed properly? The only luck I had was to prove that the error is reproduced in the new installation. Oh, I did check for zero sized files in both my 2016.4 and 2017.1 installations. There are none. I also looked at the thread regarding the DLLs. There seems to be no resolution there. Here's the output from my console: make all Building file: ../src/helloworld.c Invoking: MicroBlaze gcc compiler mb-gcc -Wall -O0 -g3 -c -fmessage-length=0 -MT"src/helloworld.o" -I../../hello_world_bsp/microblaze_0/include -mlittle-endian -mcpu=v10.0 -mxl-soft-mul -Wl,--no-relax -ffunction-sections -fdata-sections -MMD -MP -MF"src/helloworld.d" -MT"src/helloworld.o" -o "src/helloworld.o" "../src/helloworld.c" make: *** [src/helloworld.o] Error -1073741502 On the error line it says it's a C/C++ Problem. How can it be a problem with 3 lines of code? Description Resource Path Location Type make: *** [src/helloworld.o] Error -1073741502 hello_world C/C++ Problem