David1234

Members
  • Content Count

    5
  • Joined

  • Last visited

About David1234

  • Rank
    Newbie

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. I want to use the remaining flash memory to save user settings so that the user's settings persist even if power is lost. Is saving their settings to flash as they are changed the most practical way to save their settings, or is there a smarter, easier way to accomplish the same thing?
  2. Thanks Dan. I saw that entity earlier but discarded it thinking it wouldn't work because the interface didn't seem to match up. Would eqspiflash.v be the top level in a simple, non-softcore-cpu CMOD A7 project? I essentially just want to use this as a really slow memory where I just provide a WR/RD signal, address and data signals. For some reason the CMOD A7 has qspi_cs and qspi_dq[0:3] but no qspi_clk... Is the clock from something else automatically used? In general, what changes need to be made to use this in a simple, non-softcore-cpu CMOD A7 project? Thanks, David
  3. Hi, I want to use the left over flash memory that the bin file isn't using to store data. Is there an example of this being done? I haven't been able to find one. 5 ports are exposed on the CMOD A7 for this: qspi_cs and qspi_dq[0:3]. Can I use a SD card controller to write to the internal Flash like this one https://github.com/xesscorp/VHDL_Lib/blob/master/SDCard.vhd? -David
  4. I noticed that on the schematic as well. The problem with using the eFuse is that the key can be read with a microscope if an attacker mills the FPGA down to the right level. If BBRAM is used instead, the attacker would go through the same process but would need an electron microscope to read the key. Anyway, I probed several pins on the FPGA board looking for a 1.8v source to tap into. I ended up tapping into C42 on the 1.8vline and soldered a 1.5v battery and lead onto it. It works fine now and does store the key when the FPGA is powered off but I'm concerned about how much amperage the additional load is drawing. I could measure it but without a reference amperage for the key-only scenario, there is nothing to compare the current setup to. 1. Do you know how much amperage just keeping the key alive would draw? 2. What else is the 1.8v line powering? It can't be everything else because a lot of the system is 3.2v
  5. For bitstream encryption using battery-backed RAM, you are suppose to supply the Vccaux pin with voltage to keep the encryption key alive in memory. 1. Where is the Vccaux pin on the Cmod A7? (Hopefully it is not the VU pin because it would be really wasteful to power the whole FPGA just to keep the encryption key alive!) 2. What voltage is supposed to be supplied? Thanks, David