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  1. @[email protected] hey!! i think the error is in msg_appended reg bcz while comparing c code of md5 with verilog code of md5 the m reg which they used during those 4 rounds for the second block is accpeting wrong values
  2. hello here is the md5.h file and the top module through which input is applied module top; reg clk; reg rst; reg [0:511] m_in; reg [0:12] m_in_w; reg m_in_val; reg m_first; reg m_last; wire [0:127] m_out; wire m_out_val; wire ready; wire final_op; //////// instantiation of module md5 // initlal clk =1'b0; always # 5 clk = ~ clk; initlal begin rst = 1'b1; m_first = 1'b0' m_last = 1'b0; # 12; rst = 1'b0; end ///////////// input message /// inital begin m_in_val =
  3. Hello !! @jpeyron yeah actually its a simulation error. there is some bug in my rtl . I am unable to find the error hence thought this would be a better place to ask . while implementing md5, since the input message is greater than what the md5 accept as input, for the first 64 rounds it produces proper abcd values . For second rounds,the abcd value are calculated wrong due to which the whole hash value for the md5 input goes wrong. I hope I tried to answer your question
  4. hello guys, I am new to this forum . I am implementing md5 in Verilog. I am almost done with it somehow but still stuck half in a way.. can someone can help me in finding the bug in the rtl. I have referred pancham md5 source code for it and have modified a little bit as per my application. here, are the two attached files kindly help me in solving these issues. have been trying since long. I have to calculate the hash value of about 512 bytes but first of all trying from smaller input values md5.txt1.txt pancham_round.txt