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Ionut

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    Ionut got a reaction from John J in Unable to FLASH QSPI. Vivado Rev. 2022.1 5ev eval board   
    Hello,
     
    I tried to reproduce the problem on Genesys ZU-5EV, using the Hello World demo, which we recently migrated to Vivado 2023.1. I tried to program the QSPI flash from Vitis multiple times, starting from offset 0, and it completed without error every time.
    For reference, I used this repo: https://github.com/Digilent/Genesys-ZU, which I cloned and then checked out the 5EV/HELLO-WORLD/2023.1 tag.
    To rebuild the project, I followed the instructions from this page: https://digilent.com/reference/programmable-logic/genesys-zu/demos/hello-world.
    NOTE: In the respective page, the instructions marked with orange ("After recreating a Vitis workspace from source...") under the "Using the Latest Release" tab were very important in correctly compiling the sw project.
    However, when trying to boot from QSPI, I encountered the following error:
    Xilinx Zynq MP First Stage Boot Loader
    Release 2020.1   Jul  5 2023  -  17:32:44
    Reset Mode      :       System Reset
    Platform: Silicon (4.0), Running on A53-0 (64-bit) Processor, Device Name: XCZU5EV
    Digilent Genesys ZU board-specific init
    QSPI 32 bit Boot Mode
    FlashID=0x9D 0x60 0x19
    XFsbl_SpkVer: XFSBL_ERROR_INVALID_EFUSE_SELECT
    Failure at boot header authentication
    Boot Device Initialization failed 0x74
    Fsbl Error Status: 0x0
    We are investigating the issue, and we will post here as soon as we have a fix for it.
    Best Regards!
  2. Like
    Ionut got a reaction from John J in Unable to FLASH QSPI. Vivado Rev. 2022.1 5ev eval board   
    The respective tag corresponds to the latest 5EV release for the HELLO-WORLD demo project: https://github.com/Digilent/Genesys-ZU/releases/tag/5EV%2FHELLO-WORLD%2F2023.1. You can download the zip files and follow the corresponding instructions in the Genesys ZU Hello World Demo page, as an alternative to cloning the repo.
    Regarding the wrong FSBL BSP optimization flag bug, from what I know this was an issue in an older version of Vitis, regarding the -Os optimization flag for the FSBL included in the HW platform. This has since been fixed in more recent versions of Vitis. The Xilinx FSBL optimization flags are mentioned here: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842019/Zynq+UltraScale+FSBL.
     
    Best Regards!
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