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Ionut

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  1. Ionut

    Zedboard issue

    Hello, Since LD13 LED is off, it likely means the power supply on the ZedBoard has an issue - possibly VADJ. Did the board always behave like this, or it worked fine at the beginning and then at some point it started to behave like this? Also, when did you buy this board? Best Regards, Ioan.
  2. Hello, Since LD13 LED is off, it likely means the power supply on the ZedBoard has an issue. Did the board always behave like this, or it worked fine at the beginning and then at some point it started to behave like this? Also, do you remember when you bought this board? Best Regards, Ioan.
  3. Ionut

    Zedboard issue

    Hello, How were the JP7...JP11 jumpers set when you turned on the board? What I mean by this is where did the board boot from: JTAG, SD, QSPI? Is LD13 (POWER) LED also on? Also, where did you measure the VADJ voltage on the board? One good place to measure it, based on the schematic, is between pins 15 and 16 of the XADC Header (J2), as shown in the image below. Best Regards, Ioan.
  4. Hello, After plugging the power supply to the board, do you mean that LD13 (POWER) LED did not turn on? What power supply did you use: the 12V supply that came in the box with the board, or another supply? Could you try to turn the board on and off several times from the SW8 power switch, and check if the problem goes away? Also, when did you buy the respective board? Best Regards, Ioan.
  5. Hi @Andy-205, Would it be possible for you to solder on the board a wire from J5 pin 30 to J1 GNDA pad (TP1), and another wire from J1 GNDA pad (TP1) to J2 GNDA pad (TP3)? This is indicated in the image below with yellow arrows. Could you then run your test, check if the board works fine and let us know the result? Thank you! Best Regards.
  6. Hi, The OLED turn on and turn off sequences for all the above mentioned boards (Nexys Video, ZedBoard, PmodOLED) have been verified in hardware and all the updates are based on that. Best Regards.
  7. Hello, The Nexys Video OLED Demo and the ZedBoard OLED Demo have been reviewed and the OLED turn on and turn off sequences have been updated. To safely shut down the OLED display on Nexys Video, you would need to press the CPU_RESET button and wait for at least 3.5 seconds. Then you can turn off the board or reprogram it. To safely shut down the OLED display on ZedBoard, you would need to press the BTNR button and wait for at least 3.5 seconds. Then you can turn off the board or reprogram it. The above updates can be found in the latest releases for these demos: Nexys Video OLED/2022.1-2 Nexys Video OLED/2023.1-1 ZedBoard OLED/2022.1-2 ZedBoard OLED/2023.1-1 Please consult the corresponding demo pages for more details: https://digilent.com/reference/programmable-logic/nexys-video/demos/oled?redirect=1 and https://digilent.com/reference/programmable-logic/zedboard/demos/oled?redirect=1, respectively. The PmodOLED IP from vivado_library has also been reviewed and its turn on and turn off sequences updated. You can find the changes in the latest version of the master branch (https://github.com/Digilent/vivado-library). Best Regards.
  8. Hi @RisingPheonix, The MIPI_CSI2_Rx.vhd file you are referencing in your post is not the toplevel file of that IP. The toplevel is MIPI_CSI2_RxTop.vhd (linked here). Furthermore, the CSI2 RX is packaged as a Vivado IP, meaning it has a configuration GUI where you can change the settings you mentioned (please see the image below): Pixel Format - RAW8, RAW10 etc.; Pixels per Clock - 1, 2 or 4. To view this configuration GUI and edit its settings, you need to first create a block design in Vivado (if you do not have one already in your project), add this IP to the block design and then double click on the IP. After you change the settings, click "OK", connect the IP in the block design, save the block design, then press the "Validate Design" button in the upper part of the block design and the IP port widths will then be automatically updated to match your new settings. Could you try this approach to customize the IP and let me know if you encounter any issues? Best Regards, Ioan.
  9. Hi @Mustafa, As pointed out in the table you posted above, the Genesys 2 board supports on its JA and JB connectors only LVDS_25 input, not output. This means that you can receive LVDS_25 signals in the FPGA using JA and JB, but not send LVDS_25 from the FPGA JA/JB to another circuit. This restriction comes from the fact that the FPGA I/O bank connected to JA and JB is supplied from 3.3V, while LVDS_25 output requires 2.5V (Xilinx UG471, 7 Series FPGAs SelectIO Resources User Guide, Table 1-55). Since you want to output an LVDS_25 signal from the FPGA, one solution would be to use the JXADC Pmod connector instead, and set the VADJ voltage value to 2.5V using the JP6 jumper. This is necessary since VADJ supplies the FPGA bank connected to JXADC Pmod. I hope this information is helpful. Best Regards!
  10. The respective tag corresponds to the latest 5EV release for the HELLO-WORLD demo project: https://github.com/Digilent/Genesys-ZU/releases/tag/5EV%2FHELLO-WORLD%2F2023.1. You can download the zip files and follow the corresponding instructions in the Genesys ZU Hello World Demo page, as an alternative to cloning the repo. Regarding the wrong FSBL BSP optimization flag bug, from what I know this was an issue in an older version of Vitis, regarding the -Os optimization flag for the FSBL included in the HW platform. This has since been fixed in more recent versions of Vitis. The Xilinx FSBL optimization flags are mentioned here: https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18842019/Zynq+UltraScale+FSBL. Best Regards!
  11. Hello, I tried to reproduce the problem on Genesys ZU-5EV, using the Hello World demo, which we recently migrated to Vivado 2023.1. I tried to program the QSPI flash from Vitis multiple times, starting from offset 0, and it completed without error every time. For reference, I used this repo: https://github.com/Digilent/Genesys-ZU, which I cloned and then checked out the 5EV/HELLO-WORLD/2023.1 tag. To rebuild the project, I followed the instructions from this page: https://digilent.com/reference/programmable-logic/genesys-zu/demos/hello-world. NOTE: In the respective page, the instructions marked with orange ("After recreating a Vitis workspace from source...") under the "Using the Latest Release" tab were very important in correctly compiling the sw project. However, when trying to boot from QSPI, I encountered the following error: Xilinx Zynq MP First Stage Boot Loader Release 2020.1 Jul 5 2023 - 17:32:44 Reset Mode : System Reset Platform: Silicon (4.0), Running on A53-0 (64-bit) Processor, Device Name: XCZU5EV Digilent Genesys ZU board-specific init QSPI 32 bit Boot Mode FlashID=0x9D 0x60 0x19 XFsbl_SpkVer: XFSBL_ERROR_INVALID_EFUSE_SELECT Failure at boot header authentication Boot Device Initialization failed 0x74 Fsbl Error Status: 0x0 We are investigating the issue, and we will post here as soon as we have a fix for it. Best Regards!
  12. Hi John J, I apologize for answering so late to your post. Have you used our Hello World Demo as a starting point for your project (https://digilent.com/reference/programmable-logic/genesys-zu/demos/hello-world)? The FSBL inside it has been custom modified for Genesys ZU, and it might solve the problem for you. Also, what is the purpose of assigning a 1/2 GB of DDR to each core? Is it for reading/writing user data? If so, you should make sure you do not overwrite any memory area where your application code is present. lscript.ld in Vitis can help you identify and avoid the respective area. Best Regards, Ioan.
  13. Hi John J, First of all, I apologize for answering so late to your post. I realize it must be frustrating to encounter an issue and to not receive help for so long. Regarding your problem, what FSBL have you used? Have you tried our Hello World Demo as the starting point for your project (https://digilent.com/reference/programmable-logic/genesys-zu/demos/hello-world)? This demo contains a FSBL customized for the Genesys ZU; for example, it contains a workaround for a known Vivado issue. If the FSBL from our Hello World demo does not fix your issue, could you try to debug your software project in Vitis step-by-step and let me know what the debugger tells you? Best Regards, Ioan.
  14. Hi @sarvan, Could you try to rewrite the QSPI memory with the original BOOT.BIN file? Does that solve the issue? Maybe the contents on the QSPI memory got corrupted by uboot during the TFTP file transfer. But why is there a need to boot from QSPI and then switch to SD? In the Genesys ZU Getting Started Guide (https://digilent.com/reference/programmable-logic/genesys-zu/getting-started), under "Configuring and Building the Petalinux Project", it is mentioned that "While building, the Petalinux project writes the necessary files into the tftpboot directory. This allows tftp (Trivial File Transfer Protocol) to be used to boot the board over a UART connection with minimal user effort." This means that you could put on the SD card the necessary files to boot Petalinux from the start, and just boot from SD. Thus, there would be no need to use QSPI. Best Regards!
  15. Hi @sarvan, The HDMI 1.4/2.0 TX Subsystem and the HDMI 1.4/2.0 RX Subsystem IPs need purchased licenses to be able to compile bitstreams. Alternatively, there might be evaluation licenses available, but you would need to check with Xilinx if they are available. Please see the "Licensing and Ordering Information" section from the following Xilinx documents for details: https://docs.xilinx.com/r/3.1-English/pg236-v-hdmi-rx-ss/Licensing-and-Ordering-Information https://docs.xilinx.com/r/3.1-English/pg235-v-hdmi-tx-ss/Licensing-and-Ordering-Information If such licenses are not available, you would need to remove the v_hdmi_tx_ss_0 and v_hdmi_rx_ss_0 IPs from the block design. Best Regards!
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