Ionut

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  1. Hi kenken, In the VI you sent, you use two different methods to write to a measurements file: the "Write Delimited Spreadsheet" subVI I mentioned before and an Express VI for writing spreadsheets. You don't need both - any one of them would be enough. Therefore, I removed the Express VI and kept the "Write Delimited Spreadsheet". Also: - You did not wire a file path control or constant to the "file path" input, so I added a control for that; - The waveform data you wanted to wire to the "1D data" input has a red dot next to the connection to the "Write Delimited Spreadsheet
  2. Hi kenken, For logging the data in a spreadsheet, please right-click in a LabVIEW block diagram, select "Search" and look for "Write Delimited Spreadsheet". Double click on the search result, and then drag the icon that is highlighted into your block diagram. It should look like in the picture below. You then need to connect the data you want to put in a line to the "1D data" input, set the "append to file?" to T and also make sure you connect a constant or control with the file path and name to the "file path" input. This icon will create a CSV (Comma-Separated Values) file, wh
  3. Hello, T means True and logic 1, which is a high level on your DIOs. F means False and logic 0, which is a low level on your DIOs. Pretrigger time is just the time the oscilloscope input acquires signal before the actual pulse is generated; this can be useful in case you want to see an event or noise before the actual pulse. Yes, the "Wait for 20ms between reading the data and displaying + saving it." records the waveform 20ms after acquiring the waveform. Best Regards!
  4. Hi tomii, From your posts, it seems that the Pmod AD1 generates data correctly when its data outputs are not connected to the FPGA board. The series 100 ohm resistors are rather small, so any FPGA input buffer with an input impedance of tens of KOhms should not decrease the signal amplitude (by creating a voltage divider with the series 100 ohm resistor) below the minimum input high level. You could also try to enable pullup resistors on the FPGA input pins (using the | PULLUP keyword at the end of the respective NET lines in the UCF file). The pullup ressitors should not affect
  5. Hi kenken, If you look at your screenshot, from left to right: - The first circled item is the initial value for DIO14 and DIO15 (F = false = logic 0); you can leave it the way it is; - The second circled item is a flat sequence with a delay time inside; the value of the delay time is given by a local variable called "Pretrigger time (ms)", which takes its value from the front panel control with the same name. This delay is necessary so that the oscilloscope input has time to acquire the samples corresponding to the pretrigger time (i.e. the time before the rising edge that you
  6. Hi kenken, In order to wait for 20ms between reading the waveform and displaying it in the VI, you can simply add a "Wait (ms)" LabVIEW function with 20ms at its input, inside a flat sequence structure, on the wire going to the Waveform Graph. I did this in the attached VI. Also, in your VI the pretrigger time was too large (500ms, when the entire acquisition time was 500ms); there was no way to see the pulse with that pretrigger time setting. Finally, before generating the 1ms pulse, you need to wait for the pretrigger time to elapse, so that Analog Discovery can read the corre
  7. Hi kenken, I'm not sure I understand your problem. Do you want to wait for 20ms between reading the waveform and displaying it in the VI? Or do you want to acquire data using the oscilloscope input 20ms after the pulse has been generated? The case where the pulse wave is not displayed on the oscilloscope refers to the triggering problem I mentioned in my previous post. I contacted a colleague bout this, and hopefully we will have a solution soon. I have another question: which of the two attached VIs did you use: 1202_1.vi or 1202_2.vi? Best Regards!
  8. Hi kenken, I'm sorry for the delay in answering you. Generating a pulse using the digital outputs would look like in the upper part of the attached VI (see comments in the VI block diagram for details). However, using this method you would not be able to control the width of the pulse very accurately, as this is controlled by software. A desired 1ms pulse width could end up being 0.5ms or 2ms in reality. Because of this, I recommend using the method described in my previous post above (Using Waveforms SDK and LabVIEW, for example), for which the timing is controlled by hard
  9. Hi kenken, Please look at the attached LV_with_Waveforms_SDK.zip. It contains the following items: - A version of the Digilent Waveforms library I imported into LabVIEW 2015 ("DwfLibrary" folder); - A LabVIEW 2015 test project with contains this library, together with a test VI in which I started adding the functions indicated in the AnalogOut_Pulse.py source code; - The AnalogOut_Pulse.py file; - The WaveForms SDK Reference Manual.pdf manual. To complete your project, you would need to continue to add functions to the Test VI, as indicated by the AnalogOut_Pulse.py source co
  10. Hi kenken, If I understood correctly, you would like to generate a single 5V pulse? What length would that have? 1ms? In any case, the digital outputs on the Analog Discovery 2 can only generate up to 3.3V output, so they would not work for your intended use case. You can use instead one of the Waveform generator outputs to generate the pulse. However, the Digilent Waveforms VIs you are currently using do not provide the ability to reliably generate a single digital pulse. This functionality does exist in the Waveforms SDK, which is a library installed together with the Waveform
  11. Hi Duncan, From your description, it seems the "bad" start condition is recognized for some transactions, but not for others. It most likely is marginal all the time, and sometimes the ADV7611 recognizes it correctly, on other times it doesn't. But it is weird that the problem only occurs when using the FMC interface pins, but not the Pmod pins. It would be interesting to compare the FPGA implementation results between the version using FMC for the I2C lines vs. the one using the Pmod pins: - Are the two internal circuits the same (I/O buffers, gates, flip-flops)? - Are the
  12. Hi Duncan, I'm sorry for the delay in answering you. Yes, you get the Acknowledge from the slave device, but only for the prior transaction(s), for example for the 0xFD byte. For the 0x99 byte, you do not get the Acknowledge anymore. So I would ask the question: do you see a "bad" start condition (like the one from your picture for byte 0x99) for other bytes, before the 0x99 byte? Or is the "bad" start condition only appearing in that one isolated case? Best Regards!
  13. Hi kenken, Thank you for sending the VI! I managed to run your VI and ended up at the following conclusions: 1. In your oscilloscope settings, you were setting the vertical range to only 1V, too small to see the entire signal you were generating. Once I set it to a value larger than the peak-to-peak level of your signal (at 5V amplitude, peak-to-peak would be 10V, so I set the vertical range to 20V), the correct signal level appeared. 2. The default buffer size for the oscilloscope input channels which is provided by Analog Discovery 2 is 8192 samples/channel (please see ht
  14. Hello, From the waveform you attached, it seems you are issuing a stop command after the first byte (which is 0xFD), and then you attempt a start command before the second byte (which is 0x99). However, it seems to me that the SDA low pulse during the respective start command is too short, and the corresponding SCL rising edge comes rather late. Therefore, the start condition may not be properly interpreted by the ADV7611. Please see the attached picture for more info (I edited the picture you attached). I think you should try to correct the Start condition generation, and then try t
  15. Hi kenken, Would it be possible for you to attach the actual file you are showing in the screenshots (function[...].vi) to this thread? Thank you.