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Ionut last won the day on November 21 2018

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  1. You're welcome! I am glad it is working. Yes, this thread should help others trying to run the Pcam 5C demo on Zybo Z7. Best Regards, Ionut.
  2. Hello, You only have the hardware platform in SDK. You need to import the other projects from the SDK folder (fsbl, fsbl_bsp, pcam_vdma_hdmi and pcam_vdma_hdmi_bsp) into SDK, by selecting File -> Import -> General -> Existing Projects into Workspace -> Next -> Select Root Directory as \Zybo-Z7-20-pcam-5c-master\sdk -> Select the above-mentioned projects -> Finish. Then follow steps 3 through 5 from the above post. Best Regards, Ionut.
  3. Hello, The debug module for the CSI-2 IP is only used for HW debugging inside the IP itself, it is not used for setting up parameters like camera resolution. For these parameters, the AXI-Lite interface is used instead. So the messages in the UART terminal should appear regardless of the IP Debug settings. After the bitstream is generated by Vivado, please make sure you do the following: 1. Export the hardware (File -> Export -> Export Hardware -> Include bitstream) to the \Zybo-Z7-20-pcam-5c-master\hw_handoff folder, overwriting the existing file. 2. Launch SDK from Vivado (File -> Launch SDK), setting up the Exported location to \Zybo-Z7-20-pcam-5c-master\hw_handoff and the Workspace to \Zybo-Z7-20-pcam-5c-master\sdk. 3. Left click on the pcam_vdma_hdmi project and then from the top menu select Project -> Build Automatically. 4. Re-generate BSP sources for fsbl_bsp and for pcam_vdma_hdmi_bsp, by right clicking on each of these projects and selecting Re-generate BSP Sources. 5. Left click on the pcam_vdma_hdmi project. From the top icons, select Program FPGA. Then, from the top menu, select Run -> Run -> Launch on Hardware (System Debugger). The Pcam 5C demo project should then work fine. Please let me know if you encounter any issues with this. Best Regards, Ionut.
  4. Hello, I would like to make a correction to my previous statement that I didn't know of a way to reduce the size of the Pcam 5C Demo Project to fit on the Zybo Z7-10 board. Actually, there is a way to reduce the size of the design, by disabling Debug Module for the CSI-2 IP. You can perform the following steps in order to do this: 1. Download the latest version of the Pcam 5C Demo project from, in zip format. 2. Use the vivado library zip file (which includes the D-PHY and CSI-2 IPs) you previously downloaded from, or download it again. 3. Unzip the two zip files, put the vivado library in its folder under the repo folder. 4. Run the create_project.tcl script from Vivado 2017.4. 5. In the project block diagram, double-click on the MIPI_CSI_2_RX_0 IP and deselect Debug Module. Press OK. Save the project. 6. In the project settings, change the project device to xc7z010clg400-1, in order to match the Zybo Z7-10 board. 7. Report IP Status -> Upgrade Selected. Synthesis, implementation and bitstream generation should then work fine. You should then be able to run the Pcam 5C Demo project on the Zybo Z7-10 board. I hope this is helpful for you. I am sorry for the initial answer on the project size. Best Regards, Ionut.
  5. Thank you for the feedback regarding the issue when a project is created´╗┐ on Vivado in Windows then implemented on Vivado on Linux! We will look into fixing it in the demo project. Best Regards, Ionut.
  6. Hello, The Pcam 5C demo project does not fit onto the Z7-10 PL: you need a total of 18202 LUTs, and you only have 17600 on the Z7-10. In other words, at some point in the placement phase, you have 2903 available slices, while there still are 3493 slices required in order to finish placing the design. I don't know of any IP block you can remove/reduce in size in the demo project, in order to make it fit the Z7-10, while still keeping the project functional. I recommend switching to a Zybo Z7-20, where the project would fit. Best Regards, Ionut.
  7. After following the above steps, you may still see an error during Implementation which is similar to the one you initially described. This occurs because the system-level block diagram of the demo project is no longer the project top-level. To fix this error, in Vivado please right-click on the system_i block-diagram item and select "Create HDL Wrapper...". Then right-click on the HDL wrapper you just created and select "Set as Top". You will then see this HDL wrapper becoming the project top-level. If you then rerun synthesis and implementation, they should work fine. We will update the IP versions in the demo project on GitHub. Best Regards, Ioan.
  8. Hello, Could you try the following steps, in order, for building your Pcam 5C Vivado project? 1. The master vivado-library branch is missing the D-PHY and CSI-2 IPs needed for the Pcam 5C demo project. Please download the d-phy vivado-library branch instead: 2. Once you downloaded this version of the library please unzip it and copy its contents (the "if" folder, the "ip" folder, the ".gitignore" file, the "License.txt" file and the "" file) directly at the following location in your unzipped Pcam 5C Vivado project (without any additional subfolder in the path): <path to your unzipped Pcam 5C proj>\Zybo-Z7-20-pcam-5c-master\repo\vivado-library\ . 3. Clean up the project and rerun the \Zybo-Z7-20-pcam-5c-master\proj\create_project.tcl script from Vivado. 4. You may see an error in Vivado about the D-PHY and CSI-2 IPs being locked. To fix it, please run from Vivado: Tools -> Report -> Report IP Status. This will open a window saying the D-PHY and CSI-2 IPs need to be upgraded. Select "Upgrade Selected". Once this is finished, you should be able to correctly synthesize and implement the Pcam 5C Demo project. Please let me know if you encounter any other issue with the Demo Project. Best Regards, Ioan.