I'm new in FPGA and I'm trying to realize a filter using the FPGA Nexys 4 on Simulink. I have already done the Simulink circuit and export it to the Vivado Design sout as a project. Here I choose the right FPGA but i have problem with I/O Ports planning. My output of this project will be a filter which will realize the filtration of biological signal (ECG) which i will bring on JXAD input port on FPGA.
Can somebody please help me with realization in Vivado and tell me, which output can be the best after the filtration?
Your help means very much to me...