asmi

You can simply reassign a MAC address on your new system to be the same as what you had in the old one, and license will work just fine. I've done it for my license which came with my Genesys 2 board when the time came to replace my PC.

No need for any of it - you can simply change the address range in the address editor, and Vivado will figure out the rest by itself:

If you have separate instruction and data buses (like it's shown in the screenshot), you will need to change it in both places.

No need for any of it - you can simply change the address range in the address editor, and Vivado will figure out the rest by itself:

If you have separate instruction and data buses (like it's shown in the screenshot), you will need to change it in both places.

There is no BootROM in Artix. Looking at names, it looks like you're trying to synthesize one of SiFive cores, so I would recommend you ask them for support, as I assume abovementioned bootROM is going to contain some kind of startup code for their CPU core. I don't think Digilent support folks will be able to help you much on that matter, but if you want, you can of course wait until they respond.

Nowhere - they are not publicly available.

Interesting, moreso that this board went through so many revisions (I have the original Arty, back from the days when it was called simply "Arty", not "Arty A7"), and yet this wasn't changed. But I guess don't fix what ain't broken 😉

I asked one of the design engineers involved. He doesn't recall any particular reason for those vias to be unmasked and indicated it was potentially just an oversight from the engineer who did the layout. They're connected to Pmod port JC or JD.

A lot of people are prototyping DSP algorithms in Python or Matlab because they have facilities for rapid prototyping, as well as great visualization tools which allow to quickly figure out if algorithm does what it's meant to do. The key here is not the language, but the algorithm itself. That's what I think he meant.

I never used that board, but looking at specs it doesn't actually contain an audio codec, but only a microphone and a PWM output, so you can't really expect any sort of audio quality out of it, and since there is no audio input, you can't get singal into it. I would also caution you about purchasing a used FPGA boards, as FPGA being a complex device can be broken in all kinds of ways, which are not easy to diagnose.
This is just a connector, you can connect anything you want to it (provided it doesn't damage the FPGA of course). As for speed, all of those are low speed connectors, so I wouldn't be hopeful about running reliably running even moredately fast (in tens of Mbps range).

There is a potential trap in this though when your buffer is not aligned to a cache line, in that the Xil_DCacheInvalidateRange function not only invalidates the cache lines, but it also flushed them if they were updated by CPU, which could mess with the data that shares the same cache line as other variables which were modified (because cache only tracks modifications on a level of cache lines, and not individual bytes/words of data within those lines). Please refer to this post for more details: https://support.xilinx.com/s/question/0D52E00006iHjkGSAS/zynq-invalidating-a-specific-area-of-data-cache-without-flushing-its-content?language=en_US One way to combat this is to allocate your buffer statically and ensure cache line alignment, but it's not always possible.

No worries, I didn't mean to imply anything - I merely mention that because I've made that exact mistake myself more times than I'm willing to admit 🤐

After Xilinx themselves published tools and reference schematics which allow everyone to create such a tool should they want, it makes no sense for them to continue hiding it. 

Hi @pastucky,
D1 is an onsemi NSQA6V8AW5T2G.
Thanks,
JColvin

They also provide length and matching info for SYZYGY connectors as required by the specification.

Yeah, current PC RAM marketing is all over this. But since FPGA designs are very close to hardware, it's important to be more precise even with marketing materials, because I think the kind of people who buy these boards are tech savvy enough for the most part to know the difference between "marketing" MHz and real ones.

All QSPI lines except for clock are always user I/O pins, so your design can always use them, as for the clock, Xilinx provides a special primitive STARTUPE2 which allows user designs to output the clock for the QSPI flash, however specifically in the case of CMOD, they've connected another user I/O pin to the clock line such that your design can output clock through that pin directly (vs via STARTUPE2 primitive). All dual-purpose pins are completely in the user design's hands once configuration is over, FPGA itself will never interfere in any way.

That is exactly why I try to avoid writing constraints manually and instead prefer using GUI for that, as it greatly reduces chance of making silly mistakes like that one.

Well tell us then, how do you know that Arty-100 is going to be "more than enough" without knowing answers to the questions I listed. And, while you're at it, maybe you can enlighten us how that stupid tutorial which you failed to make work is relevant to this topic.

Before you select a board, you've got to figure out four things:
1. Data source - How are you going to do the capture? Is it going to be a crap ton of ADCs, or some fast multichannel ADCs, or maybe something else?
2. Data input - Whatever you settle on in (1), how this data is going to be fed into FPGA? SPI, I2S, or some custom bus? This will help you determine which and how many pins will you require from FPGA, which can disqualify a lot of FPGA boards because they won't have suitable connectivity.
3. Data processing - Once the question if bringing data into FPGA is resolved, what exactly are you going to do with that data inside FPGA? That has a major implications on a FPGA family and density that you require.
4. Data output - And finally, once you've done all the processing inside FPGA, what are going to be your outputs? This again can disqualify some boards because they lack the output method of your choice.
 
Or, and number 0 - don't ever listen to anyone saying "board X is going to be more than enough" without knowing answers to above four questions, because it will very likely end up with wasted money and frustration.

There is such an option:

 

There is such an option:

 

Yes you can, if you can fit 2.54 mm (typically) jumper leads into 2 mm pitch connector. You may have to cut down JTAG frequency due to signal integrity issues. And watch out for pinout - not all 6 pin JTAG connectors are the same!
As for exchange, you'd better talk to sales people directly via email, as I understand there are only tech support folks on this forum.

JTAG pins can't be included into XDC file because they are dedicated function pins, and can't be used for anything except JTAG.
Which is just stupid now considering Xilinx has finally published a tool which can program FTDI's EEPROM to function just like Digilent's programmer/debugger, but it would only cost about $5 in parts instead of $50+ which Digilent charges for it's solution.

JTAG pins can't be included into XDC file because they are dedicated function pins, and can't be used for anything except JTAG.
Which is just stupid now considering Xilinx has finally published a tool which can program FTDI's EEPROM to function just like Digilent's programmer/debugger, but it would only cost about $5 in parts instead of $50+ which Digilent charges for it's solution.

JTAG pins can't be included into XDC file because they are dedicated function pins, and can't be used for anything except JTAG.
Which is just stupid now considering Xilinx has finally published a tool which can program FTDI's EEPROM to function just like Digilent's programmer/debugger, but it would only cost about $5 in parts instead of $50+ which Digilent charges for it's solution.