asmi

Yes it does. You can go full 333 MHz: And I can confirm that it works in hardware just fine There is nothing to dig - just read schematics. If you can't read schematics, you'd better not get into FPGAs at all. There is a UCF file in Digilent's repository as well if you can't be bothered to type this stuff in. All DDR memories are designed for burst accesses, and so they don't perform well in true random access - and things get worse with each DDR iteration. For DDR3 at 333 MHz, the minimal CL is 5 cycles followed by 4 cycles of data (due to 8n prefetch architecture), so ~10 clocks in total (as DQS can be up to ±0.5 clock either way) just for the raw interface part. You can get a bit better latency by talking to MIG's user interface block directly (not through AXI4 adapter), but unless your design is going to push the limits of attached memory module in terms of bandwidth and latency, benefits from AXI4 are more important than the little better latency they get out of direct use of UI. I wasn't talking about this exact post - as I made clear in the post. Now, even few years down the road, you're still shilling for ZipCPU, which is just as useless now as it was few years ago. Infact I'd argue it's even more useless now as we now have free access to ARM CM1 and 3 cores, as well a a ton of RV cores out there - all for free and without the cancer of a license that is GPL.

I wonder if there is a single post by @D@n which doesn't include shameless plugs to his projects...😫 Now, directly to OP's questions: Yes you do. This is why "Clocking wizard" IP is being used (it instantiates MCMM internally). No, reference clock (clk_ref_i) is ALWAYS 200 MHz no matter what.It's fed into IDELAYCTRL blocks which control delay elements used inside MIG. You can select it in MIG wizard, but the choice is limited based on your memory's frequency. For DDR3(L) 333 MHz MIG wizard doesn't allow you to select 100 MHz as allowed input frequency due to the way MCMM is used inside MIG, as well some of its' limitations (only single fractional divider per MCMM). Since you always need to feed 200 MHz into MIG no matter what and there is only single clock source on Arty board, you will have no choice but to use MCMM, so you might as well use it to also generate input system clock. sys_rst signal is an active-low asynchronous reset, you can connect it to board's reset signal (again if polarity is right). It isn't required unless your design is supposed to withstand and properly handle system resets. It's used to bring everything to a known initial state so that memory initialization can be performed and functionality is restored if due to some bugs your HW is not working properly. I never actually tried using it, but I think it won't work out-of-box because of clocks needed to be provided - example design assumes they come directly from IO CC pins. But you can modify it to get it to work, and that shouldn't be that difficult. Same goes for status signals tg_compare_error, init_calib_complete - you can connect them to onboard LEDs provided that polarity is right (might need to inverse depending on how LEDs are wired on a board).

I'm on Windows 7 and 10. The SDK stuff seems to work as usual (except that now SDK workspaces are external to the project), not sure about SDSoC because I didn't use it before.

Try going through the link I provided above, then click "SDSoC Archive" to the left (below 2019.2 label), finally clicking 2019.1 - I was able to start downloading installer this way.

You can use Vitis to develop software for HW platforms designed in VIvado (including Microblaze). Didn't play with it yet very much beyond just creating test projects, but it seems that's the way it's supposed to work nowadays. You can still download old versions of software if you want.

It looks like Xilinx went all-Vitis. It replaces SDK, SDSoC and SDAccel. See here: https://www.xilinx.com/support/download/index.html/content/xilinx/en/downloadNav/vitis.html

Starting from 2019.2, SDK isn't included with Vivado anymore, but it's now a part of "Vitis Unified Software Platform".

When it comes to DDR3, the layout is a make or break factor. Did you do length matching as described in MIG user guide, and used controlled impedance traces as required? If not - it will never work no matter what you do. DDR3 has a fair bit of robustness built into it, and Spartan-7/Artix-7 can only drive it at mere 333/400 MHz (depending on speed grade and if you use DDR3L voltage levels or regular DDR3 ones), which is very slow for DDR3, but it doesn't mean that it will accept any random layout. From my experience, impedance is not very important at such slow speeds - especially if you have address/control terminations, but trace length matching still is. Finally I seriously doubt Digilent will give you the layout - they seem to believe is security by obscurity too much. So if you haven't done so - go and RTFM MIG user guide until you understand what exactly needs to be done in order to successfully implement DDR3(L). It's not very complicated, but attention to details is paramount.

Not yet as I'm busy with another project, but definitely will at some point!

It's got four 10.3125 Gbps lanes connected to DP connectors, that allows implementing up to DP 2.0 UHBR 10, 40 Gbps, which is good for up to 8K@30Hz or 4K@144Hz in 444 RGB mode: https://en.wikipedia.org/wiki/DisplayPort#Refresh_frequency_limits_for_standard_video But that is going to require getting your hands on DisplayPort 2.0 specification, which requires paying $5000 or $10000 a year depending on a size of your company These greedy lawyers drive me nuts!

Why private? I would like to know the answer for that question too as the main reason I bought Genesys 2 board was for its FMC connector. I think trace specifications for FMC connector should be available publicly. Xilinx for example publishes full source files for their devboards, so what's up with all this secrecy?

MIG configuration that comes from the board file only runs DDR3 at 400 MHz, while the memory can run as fast as 933 MHz, but due to the way clocking is implemented on a board I was only able to achieve approximately 900 MHz (1111 ps period). DDR3 section of the board reference page contains everything you need to know to create a MIG project yourself, or to modify pre-generated one to run memory faster. I wish the board would contain another clock source so that it would be possible to run the memory at full speed (1866 MT/s). I've used MIG a lot for my own custom FPGA boards, so I don't have any problems using it.

Analog provides free GPLed IP for use with their ADC/DACs.

JESD204B is a multigigabit serial interface, so you need a board that has a chip which have these. Cora Z7 doesn't have any. Any board which has FMC-style connector with enough bonded out MGT transceivers. Be warned though, these won't be cheap. Some JESD204B chips can run as high as 12.5 Gbps per lane, even Kintex and Virtex-7 FPGAs will be able to go that fast only at -3 speed grade. Your best bet would probably be something like Kintex Ultrascale FPGA.

The thing is - I don't really care what you think my problem is, as you obviously aren't even trying to be helpful. I have my own opinion about the people who "survived 4 decades of technology" but apparently didn't figure out that making snide and offensive comments without even knowing the people they are talking to doesn't help anyone. And no, opinions of this kind of people are best ignored. I believe I can make my own decisions about what my interests are, what do I want to do myself, and when to employ someone else's solutions. With that, and your obvious unwillingness to be helpful I kindly ask you to go do your rants elsewhere, as I'd like to receive a support that I've paid for from the vendor.