dcc

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Posts posted by dcc


  1. Hi @JColvin,

     

    Thanks for the response ... 

    I managed to figure it out eventually ... It's an HDL only project. Using Chipscope I was seeing that I could write different data (up/down count, etc) starting from address 0 and read that back correctly, but every time I opened the same SD on PC it wanted to format it. I was messing with the file system (which I don't need actually).

    HxD allows you to "opendisk" regardless of the file system, and also raw disk edit ... I found it on an MIT course. It's does the job.

    best,

    DCC

    image.thumb.png.bbed52eb22960f6ad0fc5e5014df9ada.png

     

     


  2. I am using a Nexys 4 DDR board and want to use the microSD as an external memory to read from. right now:

    • I am using HDL only
    • Want to read from SD in SPI mode as a continues loop
    • Want to write to Micro SD offline via PC

    I have an HDL code, and I am able to write to and then read-back  from the SD inside the HDL correctly, but have no idea how a data file on my computer can be turned into something on SD that  I can read properly in FPGA

    Questions:

    • What file format am I supposed to use for the  SD card? (FAT32? )
    • What tool to use? I am using HxD  http://mh-nexus.de/en/hxd/
    • I wrote a random file to the SD using the HxD, when I initiate read in FPGA, I see data, but don't know what it is! Maybe I only need to figure the address for beginning of my data???

    Thanks in advance.


  3. Hi all,

    My design is HDL only with no processor. I have large ROMs in the project and need to change the COE files all the time. IS there a way to do this without having to regenerate the core and compile from scratch?? Each change costs me 40 minutes.

    I know with Data2MEM you can do that without having to regenerate the core and compile the design from scratch (IF you have a processor), but that does not apply to my design.

    Thanks in advance for your help.

     

     


  4.  

    @jpeyron @D@n thanks ... Currently I am using pmodmic3 and a custom made board attached to the shield connector (12 bits parallel DAC). It's a pure RTL design, and I have been feeding the DAC with FPGA's ROMs and logging the data with ILA chipscope easily. I need a bigger memory to feed the DAC. and log the data back.(feeding the 12 bit DAC @ 400K sample/sec is more important) 

    I do prefer RTL and staying away from SDK, but not sure how to initialize the memory outside of SDK. 

    appreciate your comments.


  5. @D@nThanks a lot. ~1MB is what I am looking for ... I need to send a long stream of data to ARTY, on FPGA side I guess I just need to fix the clk, on PC side though, I am using tera term VT, do I just increase the Baud?

    Thanks again