Lakshmi morla

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  1. Hi @jpeyron Thank you for your suggestion regarding the issue and tried all those solutions but could not solve the issue. I just like to know whether genesys2 board contains any information regarding its version or revision i.e "H" in it. I also got one Pynq Z1 board and included board files of arty-z7-20 in path but preset for zynq processor IP in vivado 2015.2 is not working .Please suggest anything regarding this issue. With Regards, Lakshmi Morla
  2. Lakshmi morla

    GENESYS 2 BOARD

    Hello Digilent community, I have an error message which states and asks version of hard ware,This is as follow If you have information regarding this please reply "Starting FPGA-in-the-Loop test ... Generating FPGA programming file ...Passed Programming FPGA ...Passed Checking Ethernet connection ...Passed Running FIL simulation ...Failed Error:Did not receive version information from the hardware. You must have a valid connection, a compatible development board, and compatible versions of the block and FPGA programming file." This is printed over matlab console , Please help me if you know any information regarding this with regards Lakshmi Morla.
  3. Hello @elodg Thank you very much I am able to solve that issue with regards, Lakshmi Morla
  4. Hello @elodg Thank you very much for your support regarding If I stick with XDC file to be correct I have an issue stating that "ERROR: [DRC BIVC-1] Bank IO standard Vcc: Conflicting Vcc voltages in bank 33. For example, the following two ports in this bank have conflicting VCCOs: ETH_MDIO (LVCMOS15, requiring VCCO=1.500) and sysclk_p (LVDS, requiring VCCO=1.800)" This is generated by Vivado in a validation test for custom board file in matlab. I am a novice in dealing with FPGA please let me know what does that error mean.I am trying to debug it but notable to do so. Thank you for your kind support. with regards, Lakshmi Morla
  5. Hello Digilent community, My name is Lakshmi Morla and I am a student from India ,I have purchased Genesys 2 board for my research project, In regard to that i wanted to use it with matlab, where i need to prepare it for FPGA in loop. For custom board preparation i require to know regarding IO Standards of the board. Genesys2 board constrain file provides that clock is differential with LVDT IO Standard were as genesys2 board file part0_pins.xml shows that they are TMDS_33 IO Standard, and ethernet pin Mdio has LVCMOS15 (I.E=1.5V) which is not supported with LVDS type clock having 1.8v,TMDS_33 cannot be used as differetial clock( this message generated by vivado ), Please clarify on this regard of Io standards and provide ethernet Phyaddreres. Reference manual provides contradictory Io pins of Ethernet and other ports which among these files are correct. please help me and I am a novice in this regard. With Regard, Morla Lakshmi
  6. Hi @Bianca thanks for your suggestion regarding this topic, I am able to utilize this board without any worry with regards Lakshmi Morla
  7. Hello digilent community, My name is Lakshmi Morla and i am a student from india. I have purchased a pynq Z1 board through digilent. When I am using pynq image for booting and with jupyter note book, the zynq chip is heated away ,on board temperature sensor graph is crossing 67 degree celsius only after just booting and powered though USB. As i live in areas were temperature is between 43-49 degrees celsius. during summers so my question are 1) how much maximum temperature it can sustain 2 Is it normal to go such high temperatures, 3) Will chips life will deteriorate quickly, 4) is there any third party heat sink is suitable for this chip.5 This happens with pynq image loaded and other cases it s maxed out to nearly 54degree so can i use it run bare metal applications. I do not know whether to ask these questions in this forum , but please help me in this regard because i could not use this board in fear destroying chip