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  1. Hey Jon, Were you able to get it running? Best, Mike
  2. oh great! Thanks!
  3. Hey all, Might need a little more advice. I'm very new to the arty so I really appreciate the help. I find that each time I send SPI from the master device (zybo master rising edge 8 bit word), RxFifo (0x78) increments- which is what I expect. However, when I read the SPI DRR receive register, (0x6C) the value returned is always 0x00. I've tried the polled spi example offered by sdk and i get the same result. Attached is a snapshot of my spi ip in vivado, the C code in sdk that I'm using, along with the output to the UART. Any advice is appreciated. Thanks. Best, Mike
  4. oh wait i'm seeing registers change as I send in SPI.. Good sign
  5. Hey thanks that was a good find. It isn't clear to me that miso and mosi slave can share io0 but I think sck_i is probably the correct pin. In any case, I just want to be able to read at this point, so mosi_slave is the relevant pin. I played with the module in this configuration (and with ext_spi_clk changed to 50Mhz) and still haven't had much luck.. Were you able to find anything interesting? Best, Mike
  6. Thanks for the advice. Googling spi slave and reading the forums and datasheets for the axi_spi ip were one of the first things i did.. I did connect the ext_spi_clk as you suggested, but still doesn't work. It doesn't seem like too many people have explored the functionality of the spi ip in slave mode. Has anyone here had slave mode in the axi quad spi (standard mode) working for them? I'd really appreciate some input. Best, Mike
  7. Hey there, Thanks again for the help and sorry for the late reply.. I still haven't had much luck working on this. The project after compression is still too big to attach so, I just took snippets of the block diagram, constraints, and address editor in vivado. I also included some relevant sdk code. void main is in helloworld.c, but the spi_slave function is in spi_handler.c. Just to be clear, I want the spi_slave module to be able to receive spi clk, ss, etc from some other master device. As opposed to the spi_dac and spi_adc module which send and receive spi, but ultimately generate the clk and ss signals themselves. I looked at the links but it seems like all of them assume your spi module is configured to master as opposed to slave mode. Is that right? Thanks again for your help. Best, Mike ADC_spi_sendreceive.c ADC_spi_sendreceive.h DAC_spi_send.c DAC_spi_send.h helloworld.c spi_data.h spi_handler.c spi_handler.h xparameters.h EDIT: Actually I found a way to share the project. Please see the link: Best, Mike
  8. Thanks for the suggestion. I tried generating 100 MHz through a third output on the clk wizard and connecting that to ext_spi_clk on the spi_lite ips but that didn't work.. I just got the same result as above. Any other suggestions?
  9. Hi all, I'm having trouble getting a spi module set to 'slave mode' to read data. I'm working with the Arty Board and attached is my Vivado block diagram. The SPI module that I'm having trouble with is 'axi_quad_spi_0'. I've set the IP to be in standard and unchecked Master Mode in the SPI Options. I set the FIFO to 256 and Freq Ratio 16x30. I have a master device (zybo board) sending spi to these pins which I can monitor on a logic analyzer; however when reading the read reg corresponding to 'axi_quad_spi_0', I see nothing. The other registers of axi_quad_spi_0 read as follows: Reg 0x60 => 0x18a Reg 0x64 => 0x25 Reg 0x70 => 0x01 whether or not the master device is sending SPI. The output from these registers seem sort of reasonable, but I would hope the flag in reg 0x64 bit 5 to go to 0 in the case axi_quad_spi_0 clks spi data in, but it isn't, which is consistent with readreg 0x6C returning 0x00. I also tried connecting outputs of a master spi module to another slave spi module 'axi_quad_spi_2' and got the same result (see block diagram). I've also tried, the xilinx spi polled mode examples and can't seem to get those working either. See below for some relevant SDK code. Can someone tell me what I might be doing wrong? Is there something more fundamental that I don't understand? Thanks! Best, Mike #define spi_dev_id2 XPAR_SPI_2_BASEADDR void simple_receive() { int data; XSpi_WriteReg(spi_dev_id2,0x60,0x1EA); XSpi_WriteReg(spi_dev_id2,0x70,0x1); XSpi_WriteReg(spi_dev_id2,0x28,0x80); data = XSpi_ReadReg(spi_dev_id2,0x6C); printf("Lithe Buffer Simple %#02x\r\n",data); }