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  1. I installed and loaded Xilinx impact tool, and was able to successfully identify the devices both flash and FPGA. However, when programming the bit file I get an error. I think that it might have to do with the JTAG clock speed running at 30 MHz instead of the recommended 15 MHz according to the warning messages. Do you know of a way to modify the clock speed? It didn't appear to be an option on the Output->Cable Setup->Digilent USB JTAG Cable selection.
  2. Hi, I'm currently developing an embedded system using an FPGA board, which has an embedded Digilent USB JTAG programmer that enables the FPGA to be configured via the USB port on the PCIe bus. I’m trying to figure out how to use the Digilent linux configuration program “djtgcfg” to program a .bit file into the FPGA but noticed that it is not able to properly identify the Xilinx Spartan 6 chip (pn XC6SLX45T) on the board. I think the program is not able to find the Spartan device on a file “jtscdvclist.txt”, which is a lookup file containing a lot of Xilinx parts. However, I am not able to see the XC6SLX45T on the list. The closest that I could find was the XC6SLX (without the T on the end) on that list. BTW, I also see this problem when I use the Xilinx ISE impact tool plugin. Does Digilent support this particular Xilinx chip? [carsonmurray@CRS_Server_devpc104 bin64]$ ./djtgcfg init -d RTD16850149 Initializing scan chain... Found Device ID: 44028093 Found Device ID: d5058093 Found 2 device(s): Device 0: XCF16P Device 1: XC6SLX ? XILINX{ FAMILY{ ;--- FPGAs XC2S$ 00600000h 0FE00000h XC2S$E 00A00000h 0FE00000h XC3S$ 01400000h 0FE00000h XC3SD$A 06800000h 0FE00000h XC3S$AN 02600000h 0FE00000h XC3S$A 02200000h 0FE00000h XC3S$E 01C00000h 0FE00000h XC6SLX$ 04000000h 0FE00000h XC7A$T 03620000h 0FFF0000h XC7A$T 03630000h 0FFF0000h XC7K$T 03640000h 0FEE0000h XC7VX$T 03660000h 0FFF0000h XC7VX$T 03680000h 0FFE0000h XC7Z$ 03700000h 0FF00000h XCV$ 00600000h 0FE00000h XCV$E 00A00000h 0FE00000h XC2V$ 01000000h 0FE00000h XC2VP$ 01200000h 0FE00000h XC4VFX$ 01E00000h 0FE00000h XC4VLX$ 01600000h 0FE00000h XC4VSX$ 02000000h 0FE00000h XC5VFX$T 03200000h 0FE00000h XC5VLX$ 02800000h 0FE00000h XC5VLX$T 02a00000h 0FE00000h XC5VSX$T 02e00000h 0FE00000h XC5VTX$T 04500000h 0FE00000h XC6VCX$T 042c0000h 0FFE0000h XC6VLX$T 04240000h 0FFE0000h XC6VLX760T 04230000h 0FFF0000h XC6VSX$T 04280000h 0FFE0000h XC6SLX${ TYPE = FPGA IRLEN = 6 ALG = 5 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 JPROGRAM 0000000Bh ;---001011 JSHUTDOWN 0000000Dh ;---001101 } DEVICES{ 4 04000093h 0FFFFFFFh 16 04002093h 0FFFFFFFh 25 04004093h 0FFFFFFFh 45 04008093h 0FFFFFFFh 150 0401D093h 0FFFFFFFh } } Thanks, Carson