Carson

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  1. I'm writing a USB to JTAG programmer using Adept SDK APIs. Does anyone know if there is a way to set the FT232H chip IO drive strength which appears to have (4ma, 8ma, 12ma, or 16ma) options available?
  2. Dan, I'm able to load that same .bit file successfully using iMPACT and a Xilinx Platform II cable so I think that the power supplies are okay. Carson
  3. Hi, I'm running linux Centos 7 and installed Xilinx ISE 14.7, Adept runtime 2.16.6-x86_64, and libCseDigilent_2.5.2-x86_64 (Digilent plugin for impact). The hardware that I am trying to program via JTAG is a Xilinx Spartan 6 FPGA board with an on board FTDI FT232H USB to JTAG chip. As best that I can tell, it looks like iMPACT loads the .bit file successfully (CRC check passes), however it appears to fail on the startup sequence with the DONE pin stuck on 0. I've tried changing the various startup parameter options that ISE 14.7 uses to build the .bit file, however I still get the same results. From the Xilinx user manual, it looks like the startup sequence requires about 8 clock cycles of JTAG clock to get going after the bit file loads. I'm wondering if the JTAG stops after the bit file load is complete instead of continuing for another 8 cycles... Any ideas? Release 14.7 - iMPACT P.20131013 (lin64) Copyright (c) 1995-2013 Xilinx, Inc. All rights reserved. Preference Table Name Setting StartupClock Auto_Correction AutoSignature False KeepSVF False ConcurrentMode False UseHighz False ConfigOnFailure Stop UserLevel Novice MessageLevel Detailed svfUseTime false SpiByteSwap Auto_Correction AutoInfer false SvfPlayDisplayComments false INFO:iMPACT - Digilent Plugin: Plugin Version: 2.5.2 INFO:iMPACT - Digilent Plugin: Opening device : "SN:2516380000BE". INFO:iMPACT - Digilent Plugin: User Name: RTD17720118 INFO:iMPACT - Digilent Plugin: Product Name: Digilent PS2 INFO:iMPACT - Digilent Plugin: Serial Number: 2516380000BE INFO:iMPACT - Digilent Plugin: Product ID: 31000154 INFO:iMPACT - Digilent Plugin: Firmware Version: 010B INFO:iMPACT - Digilent Plugin: JTAG Port Number: 0 INFO:iMPACT - Digilent Plugin: JTAG Clock Frequency: 1000000 Hz Identifying chain contents...'0': : Manufacturer's ID = Xilinx xc6slx45t, Version : 4 INFO:iMPACT:1777 - Reading /opt/Xilinx/14.7/ISE_DS/ISE/spartan6/data/xc6slx45t.bsd... INFO:iMPACT:501 - '1': Added Device xc6slx45t successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- '1': : Manufacturer's ID = Xilinx xcf16p, Version : 13 INFO:iMPACT:1777 - Reading /opt/Xilinx/14.7/ISE_DS/ISE/xcfp/data/xcf16p.bsd... INFO:iMPACT:501 - '1': Added Device xcf16p successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- done. Elapsed time = 0 sec. Elapsed time = 0 sec. Elapsed time = 0 sec. Elapsed time = 0 sec. '2': Loading file '/root/workspace_latest/NRL-LIB/FPGA/fpga35s6045_top.bit' ... done. UserID read from the bitstream file = 0x12345678. Data width read from the bitstream file = 1. ---------------------------------------------------------------------- INFO:iMPACT:501 - '2': Added Device xc6slx45t successfully. ---------------------------------------------------------------------- ---------------------------------------------------------------------- Maximum TCK operating frequency for this device chain: 15000000. Validating chain... Boundary-scan chain validated successfully. '2': IDCODE is '01000100000000101000000010010011' '2': IDCODE is '44028093' (in hex). '2': : Manufacturer's ID = Xilinx xc6slx45t, Version : 4 Elapsed time = 0 sec. Maximum TCK operating frequency for this device chain: 15000000. Validating chain... Boundary-scan chain validated successfully. '2': Programming device... LCK_cycle = NoWait. LCK cycle: NoWait done. '2': Reading status register contents... [0] CRC ERROR : 0 [1] IDCODE ERROR : 0 [2] DCM LOCK STATUS : 1 [3] GTS_CFG_B STATUS : 0 [4] GWE STATUS : 0 [5] GHIGH STATUS : 0 [6] DECRYPTION ERROR : 0 [7] DECRYPTOR ENABLE : 0 [8] HSWAPEN PIN : 1 [9] MODE PIN M[0] : 0 [10] MODE PIN M[1] : 0 [11] RESERVED : 0 [12] INIT_B PIN : 1 [13] DONE PIN : 0 [14] SUSPEND STATUS : 0 [15] FALLBACK STATUS : 0 INFO:iMPACT:2219 - Status register values: INFO:iMPACT - 0010 0000 1000 1000 INFO:iMPACT:579 - '2': Completed downloading bit file to device. INFO:iMPACT:188 - '2': Programming completed successfully. LCK_cycle = NoWait. LCK cycle: NoWait INFO:iMPACT - '2': Checking done pin....done. '2': Programming terminated. DONE did not go high. Elapsed time = 12 sec. ---------------------------------------------------------------------- ---------------------------------------------------------------------- Xilinx_Config_UserManual_ug380_config.pdf
  4. I installed and loaded Xilinx impact tool, and was able to successfully identify the devices both flash and FPGA. However, when programming the bit file I get an error. I think that it might have to do with the JTAG clock speed running at 30 MHz instead of the recommended 15 MHz according to the warning messages. Do you know of a way to modify the clock speed? It didn't appear to be an option on the Output->Cable Setup->Digilent USB JTAG Cable selection.
  5. Hi, I'm currently developing an embedded system using an FPGA board, which has an embedded Digilent USB JTAG programmer that enables the FPGA to be configured via the USB port on the PCIe bus. I’m trying to figure out how to use the Digilent linux configuration program “djtgcfg” to program a .bit file into the FPGA but noticed that it is not able to properly identify the Xilinx Spartan 6 chip (pn XC6SLX45T) on the board. I think the program is not able to find the Spartan device on a file “jtscdvclist.txt”, which is a lookup file containing a lot of Xilinx parts. However, I am not able to see the XC6SLX45T on the list. The closest that I could find was the XC6SLX (without the T on the end) on that list. BTW, I also see this problem when I use the Xilinx ISE impact tool plugin. Does Digilent support this particular Xilinx chip? [carsonmurray@CRS_Server_devpc104 bin64]$ ./djtgcfg init -d RTD16850149 Initializing scan chain... Found Device ID: 44028093 Found Device ID: d5058093 Found 2 device(s): Device 0: XCF16P Device 1: XC6SLX ? XILINX{ FAMILY{ ;--- FPGAs XC2S$ 00600000h 0FE00000h XC2S$E 00A00000h 0FE00000h XC3S$ 01400000h 0FE00000h XC3SD$A 06800000h 0FE00000h XC3S$AN 02600000h 0FE00000h XC3S$A 02200000h 0FE00000h XC3S$E 01C00000h 0FE00000h XC6SLX$ 04000000h 0FE00000h XC7A$T 03620000h 0FFF0000h XC7A$T 03630000h 0FFF0000h XC7K$T 03640000h 0FEE0000h XC7VX$T 03660000h 0FFF0000h XC7VX$T 03680000h 0FFE0000h XC7Z$ 03700000h 0FF00000h XCV$ 00600000h 0FE00000h XCV$E 00A00000h 0FE00000h XC2V$ 01000000h 0FE00000h XC2VP$ 01200000h 0FE00000h XC4VFX$ 01E00000h 0FE00000h XC4VLX$ 01600000h 0FE00000h XC4VSX$ 02000000h 0FE00000h XC5VFX$T 03200000h 0FE00000h XC5VLX$ 02800000h 0FE00000h XC5VLX$T 02a00000h 0FE00000h XC5VSX$T 02e00000h 0FE00000h XC5VTX$T 04500000h 0FE00000h XC6VCX$T 042c0000h 0FFE0000h XC6VLX$T 04240000h 0FFE0000h XC6VLX760T 04230000h 0FFF0000h XC6VSX$T 04280000h 0FFE0000h XC6SLX${ TYPE = FPGA IRLEN = 6 ALG = 5 COMMANDS{ CFG_OUT 00000004h ;---000100 IDCODE 00000009h ;---001001 CFG_IN 00000005h ;---000101 JSTART 0000000Ch ;---001100 BYPASS 0000003Fh ;---111111 JPROGRAM 0000000Bh ;---001011 JSHUTDOWN 0000000Dh ;---001101 } DEVICES{ 4 04000093h 0FFFFFFFh 16 04002093h 0FFFFFFFh 25 04004093h 0FFFFFFFh 45 04008093h 0FFFFFFFh 150 0401D093h 0FFFFFFFh } } Thanks, Carson