Antonio Rios

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  1. Thanks for your response. Attached you can find my system-top.dts file (system-top.dts). In this file I add the axi_dma_test node. Attached you can find a screen shot of my block diagram. The used clock (FCLK_CLK0) for my design is 50MHz and it is generated by the precessing system module. The idea of using the axi dma test is to check that everything is well configure in order to use the xilinx driver for axi dma. Now I manage the axi dma module form the user space, writing and reading the control/status registers of the axi dma mapped on /dev/mem. This solution is fine for testing but now I need to use the real driver in order to make my solution more robust. Best,
  2. Hi @sbobrowicz Thanks for your reply. Yes, I imported my hdf into my petelinux proyect. Attached you can find my pl.dtsi file (pl.dtsi), where I have changed interrupt values according to the xilinx axi dma wiki page ( I have an axi_dma core in my vivado block design, where the dma channel are connected like a loopback. The message "xilinx-vdma 40400000.dma: Xilinx AXI VDMA Engine Driver Probed!! " appears because from the petalinux version 2016.3, all axi dma drivers are merger in the same driver. On the wiki (, at the end of the page you can find a change log about that: Deleted the AXI DMA/CDMA driver and Merged the AXI DMA/CDMA code with the VDMA driver Merged all the 3 DMA's drivers into a single driver I don't know if I'm loosing something in the petalinux configuration. I'm working on this issue from long time but I have no idea what I'm doing wrong. Any idea? Best,
  3. Hi everyone, I'm trying to use the axi_dma xilinx driver in order to make transfer between PS and PL in both way. I posted this issue on the xilinx forum but I didn't get any response. This is the link: Now I'm using the version 2016.3 for both software, Vivado and Peralinux. Any idea?? I have looked for across the web but I cannot be able to manage the axidma engine. Thanks in advance Best,