paolo_unice

Members
  • Content Count

    10
  • Joined

  • Last visited

1 Follower

About paolo_unice

  • Rank
    Member

Recent Profile Visitors

The recent visitors block is disabled and is not being shown to other users.

  1. paolo_unice

    HDL Coder with Zedboard

    Thank you @D@n, I understand your point of view. I want to find a solution in Simulink because someone requires it to me, and I'm more skilled with the Mathworks products. I tried to open the Vivado project created by Simulink and you're right, it's quite impossible to read it. I hope I will find a solution. Bye, Paolo.
  2. paolo_unice

    HDL Coder with Zedboard

    Hi everyone; I want to build a real-time control system using the Zedboard. I want to connect the board using the Pmod modules to the actuator and the sensor, and I want to ask you if it is a good idea to do it throught the Simulink HDL Coder. So, My first question is: is it possible to interface the Pmod AD/DA with the board using simulink coder? And how? I did it in Vivado in VHDL but now I want to build the overall system in Simulink and I don't have idea how to do it. Thank you so much. Paolo
  3. paolo_unice

    PmodDA2 & PmodAD1 Data Acquisition ZEDBOARD

    Ok; I received the information. And, if I want to save in the DDR3 memory the information received from the PmodAD1, and after read this information for PmodDA2; what can I do? What is the way to follow? I'm sorry but I started working with FPGA 10 days ago and I have a lot of doubts. Thank you for your patience!
  4. paolo_unice

    PmodDA2 & PmodAD1 Data Acquisition ZEDBOARD

    Thank you @Notarobot @D@n @jpeyron! The programs are working for PmodDA2 and PmodAD1. I understand the fact about the I/O constraints and now I want to test the two communications togheter. So, I connect the two Pmod qt the board. How can I program the board with the two VHDL codes for DA2 and AD1? Is it possible? What can I do?
  5. paolo_unice

    PmodDA2 & PmodAD1 Data Acquisition ZEDBOARD

    Is it correct if I set this in I/O constraints? set_property PACKAGE_PIN Y9 [get_ports CLK] So, I say to the input port CLK to take the signal from the pin Y9 (100Mhz clock of the board). Is it correct? Thank you; Paolo.
  6. paolo_unice

    PmodDA2 & PmodAD1 Data Acquisition ZEDBOARD

    I did everything; I programmed the board and now what can I do to test if the program effectively work on the board? I want just to see if the PINs related to D1 and D2 gives the correct response. How can I send a test input to the Zedboard?
  7. paolo_unice

    PmodDA2 & PmodAD1 Data Acquisition ZEDBOARD

    Thank you @D@n! Now I understand. Can you tell me something about time constraints? When and why I have to define them?
  8. paolo_unice

    PmodDA2 & PmodAD1 Data Acquisition ZEDBOARD

    I use Zedboard xc7z020-clg484-1. And Vivado. It is not correct to use that file for this board? I'm sorry but I'm really a beginner and I don't understand a lot about it.
  9. paolo_unice

    PmodDA2 & PmodAD1 Data Acquisition ZEDBOARD

    Thank you for the answers. I found the code for PmodDA2 (in attach) for Nexys2. I just modified the DivFactor (2 instead of 3). You think that is it good? I have to set some I/O constraints in Vivado in order to select the output port to connect the Pmod? Can you explain me something about it please? Thank you. Paolo DA2RefComp.vhd
  10. paolo_unice

    PmodDA2 & PmodAD1 Data Acquisition ZEDBOARD

    Hi everyone; I'm a beginner with FPGA. I have a Zedboard xc7z020-clg484-1 and two converters PmodDA2, PmodAD1. Do you have a working VHDL code to interface these devices with the board? Thank you!