Ben

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Everything posted by Ben

  1. Hi Dan Thank you for your reply, I will certainly take a look at your simulator. I actually have it working now, with exactly half of the ASCII table. Everything with bit 4 set just displays a block character. Everything with bit 4 unset works perfectly. I'm stumped haha. Ben
  2. Hi all I have a very simply UART TX/RX pair I have built in Verilog, and have been struggling to get them to function on the Arty Board. I can connect the two together to form a simple "echo" function, where any received RX data is immediately sent out on the TX module, but beyond that I can't correctly see the values I send to the Arty. I tried simply piping the received byte to the LEDs on the Arty board, but the values lit up do not correspond at all to the ones I expect. Sending the character string "AaA" does not make the ascii encodings for "A" and "a" appear on the LEDs. However, I do get the right characters echoed back to my PuTTY terminal. My code for the project can be found here: https://github.com/ben-marshall/uart You'll need: rtl/uart_rx.v , rtl/uart_tx.v, rtl/impl_top.v and constraints/default.xdc to re-create the project. I'm using Vivado 2016.4 on Ubuntu 16.04. Thanks, Ben