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  1. I'm using the Nexys Video board, and I followed this tutorial and use JTAG to program it. However, data and program are lost when power is off and I have to re-configure the board. What should I do to have the program launched automatically every time the power is on? Through the tutorial mentioned above, I understand that I need a Quad SPI Flash, should I just follow the section N°5? By the way, once the program is stored, how to modify? If I use a QSPI flash, do I just need to create a new bitstream and repeat the instructions in section n°5?
  2. Yes, I confused the uppercase/lowercase of 'x' in the top level and the XDC file as I thought it didn't matter, Thank you.
  3. In my project, I need to use the UART ports on the NexysVideo board to transmit signals to a Raspberry. I defined 2 signals Rx_raspi as an in std_logic and Tx_raspi as an out std_logic, and in the XDC file, they are defined as: set_property -dict { PACKAGE_PIN AA19 IOSTANDARD LVCMOS33 } [get_ports Rx_raspi ]; set_property -dict { PACKAGE_PIN V18 IOSTANDARD LVCMOS33 } [get_ports Tx_raspi ]; while implementing, errors show that no ports matched. [Vivado 12-584] No ports matched 'Tx_raspi'. [Vivado 12-584] No ports matched 'Rx_raspi'. [Common 17-55] 'set_property' expects at least one object. [Common 17-55] 'set_property' expects at least one object. What was wrong?
  4. I mean VADJ_EN and SET_VADJ(1:0)
  5. @zygot, Could you tell me how to configure Vadj voltage? More concretely, how can I set VADJ_EN and T_VADJ(1:0)?
  6. Hello everyone, I'm migrating my ancient project from the Nexys2 to the Nexys Video, in UCF, the Hirose FX2 signals on the Nexys2 were declared as LVTTL I/O standards, while the FMC signals are declared as LVCMOS in the XDC files provided on the Digilent Resource Center. After doing some researches, I know that LVTTL and LVCMOS differ by their input voltages. In the paragraph of Power Supplies in datasheet of the Nexys Video, il mentions " An FPGA design can dynamically change the VADJ voltage to suit a certain FMC mezzanine card or application. Care must be taken to disable the regulator first by bringing "VADJ_EN" low, setting "SET_VADJ(1:0)" and enabling the regulator again. Please note that for proper voltage levels in digital signals connected to VADJ-powered FPGA banks (ex. user push-buttons), the correct I/O standard still needs to be set in the design user constraints (XDC or UCF file). See the schematic and/or the constraints file to determine which signals are in VADJ-powered banks. The provided master UCF and XDC files assume the default VADJ voltage of 1.2V, declaring LVCMOS12 as the I/O standard for these signals." The VADJ power rail requires special attention. It is a programmable voltage rail that powers the FMC mezzanine connector, user push-buttons, switches, XADC Pmod connector, and the FPGA banks connected to these peripherals (banks 15, 16). Dose it mean that if I set the SET_VADJ(1:0) on 11, the VADJ voltage = 3.3V, so the FMC signalss' I/O standards can be set as LVTTL?
  7. Hi @JColvin, Could you tell me that the FMC conncetor on the Nexysvideo board is a female or male socket. Where can I buy the other side of this connector? Thank you.
  8. @JColvin, Thank you for your answer, in the last version of the project, we have used 26 Pmod pins, 40 Hirose FX2 pins, 3 slide buttons, 4 LEDs and 2 pushbuttons in the Nexys 2 board. We suggest also adding new functions to the project, such as saving data in a sliding table, so more connectors are needed.
  9. Hello everybody, I'm a trainee in digital electronics, i should achieve a migration of VHDL codes from the Digilent Nexys 2 which is obsolete to another board, after some researches, I would like to work with the Nexys4DDR board. However, there is a problem of the number of connectors in the Nexys4DDR, in my project, I need at least 40 pins for my signals, it was possible with the Nexys2 thanks to the Hirose FX2 connector which disappears in the new Nexy boards. Should I choose another FPGA board or add an expansion to the Nexys4? In the last case, will there be synchronization problems?