jocularjj

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  1. to my knowledge I am pointing to the IP from diligent . To the left is the pointer in my IP catalog to D:\IP\ to the right I have D:\IP\pmods with the list of pmods that are given Adding the whole file to the repository doesn't seem to help either [BD 41-51] Could not find bus definition for the interface: PmodOLEDrgb_out [BD 41-49] Could not find abstraction definition for the interface: PmodOLEDrgb_out [BD 41-51] Could not find bus definition for the interface: Pmod_out [BD 41-49] Could not find abstraction definition for the interface: Pmod_out [BD 4
  2. when I try that I get a list of error messages below. [BD 5-106] Arguments to the connect_bd_intf_net command cannot be empty. [BD 41-51] Could not find bus definition for the interface: Pmod_out [BD 41-49] Could not find abstraction definition for the interface: Pmod_out [BD 41-49] Could not find abstraction definition for the interface: Pmod_out [BD 41-51] Could not find bus definition for the interface: Pmod_out [BD 41-49] Could not find abstraction definition for the interface: Pmod_out [BD 41-49] Could not find abstraction definition for the interf
  3. I have multiple drivers that are hanging around in the IP report although there are only one in my block diagram. Here is the OLEDrgb error message from the OLEDrgb driver that was attached earlier to this thread.
  4. The Port still doesn't appear on the oledrgb output port isn't working with the downloaded files in 2016.2 or 2016.4 with either file. Showing Board file and IP catelog and pmod Missing port connectors Missing output port doesn't add in any of the ways described in the previous posts(You can see that the output pmod is on the bt mod not the oled) In the other 2016.4 the project is not able to compile like 2016.2. The port doesn't connect to the oledrgb output port either. When selecting the add there is no known valid portions of the oled disp
  5. Yes board files are in image. Yes I have used the right click method on ports in board file and added that way. Yes I generated this base through a microserver tutorial on digilinc. I will try the block diagrams. thanks for letting me look at them. opening the files it looks like the pmodOLEDrgb I pulled from the from digilent are a newer version than yours. after updating the drivers it looks like I am still getting critical warnings and Jb or JC falls off of PMOD OLEDrgb. I can update pictures tomorrow.
  6. Thanks for the quick reply I am using Nexsys DDR board Block diagram is attached. Clk3 from ip wiz which is 50 Mhz is attached to ext_spi_clk AXI aclk and axi aclk2 is 100 Mhz from the clock wizard also. I am using 2016.2 and have more problems when I tried 2016.4 of vivado, and Win 8.1. I do have the board updated in the vivado directory and I am pointing to the ip repo in ip catalog. also I am getting errors that don't let me attach the ports from the two blocks to be external, I attached a new image to show my method for connecting in addition to control t an
  7. I and 2 other partners are having problems with the PmodOLEDrgb block diagram. When it is in the IP flow pops up when the project is open, and below shows the list of errors. I think the Pmod has an error in it, which even when I open the block diagram. When trying to regenerate the block diagram: ERROR: [BD 5-106] Arguments to the connect_bd_intf_net command cannot be empty. ERROR: [Common 17-39] 'connect_bd_intf_net' failed due to earlier errors. endgroup Opening the block diagram: [BD 41-51] Could not find bus definition for the interface: Pmod_out [BD 41-49]
  8. It was 2 pin, but I solved it by right clicking the DDR2 SDRAM in the external memory on the board. I had to connect the DDR2 SDRAM manually. Thanks for looking into it
  9. Hey I have followed the tutorial and I have the memory unit not enumerate correctly. It's block by the same name appears as a 2 port block. tutorial from nexys-4-ddr-getting-started-with-microblaze-servers found at https://reference.digilentinc.com/learn/programmable-logic/tutorials/nexys-4-ddr-getting-started-with-microblaze-servers/start I have the problem when I am adding the core "memory interface generator" in step 3.1 works and is per the figure, but the auto configuration of the block in step 4 doesn't appear to work because the figure in 4.2 looks different. I have started th