rb251415

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  1. @D@n, The issue was that I put 's_axis...' and 'm_axis...' in my entity. This caused a conflict because they went nowhere. I just created signals 'm_axis_data_tvalid' and 'm_axis_data_tdata'. It generated a bitstream and ran. It sounds like a rhythmic tapping sound. I will review your initial information on the s_axis_phase_tdata input and do a few more trials. Thanks
  2. @D@n, Out of frustration I tried to generate a bitstream even though the simulation failed. I got an error message "...17 out of 22 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned value." I guess It does not like line 81 s_axis_phase_tvalid => '1', I created a signal tvalid and tied it to my enable switch. The simulation complied and ran ( I forced clk to a 10ns cycle clock, swt to '1', rst to '1' for 5ns then '0'). My simulation ran and I got a dataout signal. But now it will not generate a bitstream. I thought maybe there was a mismatch between the aclk, used with DDS, and clkdiv, used with my PWM output. I changed my PWM to use clk and still no luck. Here is my top_io code for your review. Any ideas are welcomed. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values -- use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Wave_top is port (clk, swt, rst :in std_logic; dataout, senb: out std_logic; s_axis_phase_tvalid : IN STD_LOGIC; s_axis_phase_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tdata : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); end Wave_top; architecture Behavioral of Wave_top is signal clkdiv: std_logic; signal cntr: std_logic_vector(31 downto 0); signal PWM_IN: std_logic_vector(10 downto 0); signal PWM_ACC: std_logic_vector(11 downto 0):= (others => '0'); signal PWM_OUT: std_logic; signal tvalid: std_logic; COMPONENT dds_compiler_0 PORT ( aclk : IN STD_LOGIC; s_axis_phase_tvalid : IN STD_LOGIC; s_axis_phase_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; begin senb <= swt; tvalid <= swt; DIVIDER:process(clk, rst) begin if rst = '1' then cntr <= (others=> '0'); else if (rising_edge(clk)) then cntr <= cntr + 1; end if; end if; end process; clkdiv <= cntr(13); inst_1: dds_compiler_0 port map ( aclk => clk, s_axis_phase_tvalid => tvalid, s_axis_phase_tdata => cntr(31 downto 24), m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tdata => m_axis_data_tdata); PWM_IN <= m_axis_data_tdata(10 downto 0); PWM:process(clk,PWM_IN) begin if rising_edge(clk) then PWM_ACC <= ("0" & PWM_ACC(10 downto 0)) + ("0" & PWM_IN); end if; end process; dataout <= PWM_ACC(11); end Behavioral;
  3. This is a response question to an earlier thread that I was not able to continue. I did as you suggested. I used the 100MHz clock as aclk. I set s_axis_phase_tvalid to '1', and I used the top bits (Most Significant Bits) of my counter (cntr) for s_axis_phase_tdata. It doesnt show any error, but it will not compile. "ERROR: [VRFC 10-665] expression has 6 elements ; formal s_axis_phase_tdata expects 8" I've tried it with 6, 8 and even all 32-bits and I get the same failure. Code: inst_1: dds_compiler_0 port map ( aclk => clk, s_axis_phase_tvalid => '1', s_axis_phase_tdata => cntr(31 downto 24), -- this is line 82 of Wave_top.vhd m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tdata => m_axis_data_tdata); LOG DATA: Vivado Simulator 2016.4 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto 0fc31941c582466d8f4474edc8fb8bef --debug typical --relax --mt 2 -L xbip_utils_v3_0_7 -L axi_utils_v2_0_3 -L xbip_pipe_v3_0_3 -L xbip_bram18k_v3_0_3 -L mult_gen_v12_0_12 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_3 -L xbip_dsp48_multadd_v3_0_3 -L dds_compiler_v6_0_13 -L xil_defaultlib -L secureip -L xpm --snapshot Wave_top_behav xil_defaultlib.Wave_top -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-665] expression has 6 elements ; formal s_axis_phase_tdata expects 8 [C:/Users/Toshiba-/coregen_sinewave/coregen_sinewave.srcs/sources_1/new/Wave_top.vhd:82] ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit wave_top in library work failed.
  4. I did as you suggested. I used the 100MHz clock as aclk. I set s_axis_phase_tvalid to '1', and I used the top bits (Most Significant Bits) of my counter (cntr) for s_axis_phase_tdata. It doesnt show any error, but it will not compile. "ERROR: [VRFC 10-665] expression has 6 elements ; formal s_axis_phase_tdata expects 8" I've tried it with 6, 8 and even all 32-bits and I get the same failure. Code: inst_1: dds_compiler_0 port map ( aclk => clk, s_axis_phase_tvalid => '1', s_axis_phase_tdata => cntr(31 downto 24), -- this is line 82 of Wave_top.vhd m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tdata => m_axis_data_tdata); LOG DATA: Vivado Simulator 2016.4 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto 0fc31941c582466d8f4474edc8fb8bef --debug typical --relax --mt 2 -L xbip_utils_v3_0_7 -L axi_utils_v2_0_3 -L xbip_pipe_v3_0_3 -L xbip_bram18k_v3_0_3 -L mult_gen_v12_0_12 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_3 -L xbip_dsp48_multadd_v3_0_3 -L dds_compiler_v6_0_13 -L xil_defaultlib -L secureip -L xpm --snapshot Wave_top_behav xil_defaultlib.Wave_top -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-665] expression has 6 elements ; formal s_axis_phase_tdata expects 8 [C:/Users/Toshiba-/coregen_sinewave/coregen_sinewave.srcs/sources_1/new/Wave_top.vhd:82] ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit wave_top in library work failed.
  5. I am trying to determine if and how a Vivado IP Core can be used to create and audible tone. I have been reviewing the DSS Compiler 6.0 product guide and simulation tutorial ug937. I have configured it as shown in the attached image. I understand the sine wave output should be bits (10 downto 0) of "m_axis_data_tdata". It is asking for s_axis_phase_tvalid, s_axis_phase_tdata for input. I cannot seem to get a clear understanding of what these are. Can someone explain in layman's terms? I also created a clock divider to drop aclk down to 12kHz as an attempt the get my sine wave into the audible range. I get no output on the board or in the simulator. Ideas???
  6. Thanks again! I will review your info,... and probably be back with more questions. Have a GREAT DAY!
  7. BINGO! That was it! I'm a little embarrassed that I read that so wrong! Thank you! Next question...Can this also be used for integer values or do I need a std_logic_vector?
  8. I am getting 3.3v across JB3:B15 and 1.62v across JB1:A14
  9. I created an output bit sound enable {senb} and force it high when the counter enable is high. I tied it to board output JB3:B15 ##Pmod Header JB ##Sch name = JB1 set_property PACKAGE_PIN A14 [get_ports {dataout}] set_property IOSTANDARD LVCMOS33 [get_ports {dataout}] ##Sch name = JB3 set_property PACKAGE_PIN B15 [get_ports {senb}] set_property IOSTANDARD LVCMOS33 [get_ports {senb}] I ran the simulation on Aldec-HDL and it shows senb to be operating correctly. I still do not get sound. I will check for voltage at JB3:B15 next. Any other ideas?
  10. I am working on a school project making a sound (tone/ multi-tone) generator using a BASYS3 and Vivado. I am having trouble getting the sound part out. As a test I wrote a simple VHDL program to create a 357Hz square wave. I declared an output bit 'dataout'. I ran a simulation using Aldec-HDL Student Edition and I am getting the output squareware. I am using the PmodAMP2 connected to JB1 top row. In my xdc file I have dataout assigned to A14 ##Pmod Header JB ##Sch name = JB1 set_property PACKAGE_PIN A14 [get_ports {dataout}] set_property IOSTANDARD LVCMOS33 [get_ports {dataout}] I have connected stereo headphones to the PmodAMP2 jack. I get NO sound output. To test my board and program I set all the leds to light thru the counter. They work and flicker at different rates relative to where they are in the counter. But still no sound. What I am doing wrong? Is PmodAMP2 the right add-on to use or should I try PmodR2R? It shouldn't matter, but are the headphones causing the issue? The ref. sheet says 2.5 watt output. I also have questions about outputting integer values to the PmodAMP2 or PmodR2R. The BASYS3 and Pmod Reference manuals are not helping. One of my planned files has an integer range -92000 to 92000 (roughly). Please help!