rb251415

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  1. @hamster, @D@n, Thanks! It worked like a charm. I had to adjust my RADIX in the simulator. The added DC component made my PWM waveform look a little different in the simulator, but the output from the board still sounds the same. Will put them on the scope next. Thanks again! You guys ROCK!
  2. This is my third post for my Soundbox project. I have sucessfully created a sinewave output from the DDS Compiler 6.0. I am running the Vivado Simulator and the m_axis_data_tdata shows a nice smooth wave. I have it set for analog waveform with radix as signed decimal. I have a PulseWidth Modulator process set to output to a single bit, but have been getting un-predicted results. I setup and attached the PMODR2R 8-bit digital to analog converter to see what the actual signal looks like. I have then attached my oscilloscope to the analog output. I have been getting un-predicted output on my scope. I was playing with the simulator and stumbled upon the output I am getting on my scope. It appears to be the "unsigned decimal" output. How can I correct this? How can I get the "signed" analog output from my BASYS3 PMODR2R? Here is the code: library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_SIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values -- use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Wave_top is port (clk, swt, rst :in std_logic; analogout: out std_logic_vector(7 downto 0); dataout, senb: out std_logic ); end Wave_top; architecture Behavioral of Wave_top is signal clkdiv: std_logic; signal cntr: std_logic_vector(31 downto 0); signal PWM_IN: std_logic_vector(7 downto 0); signal PWM_ACC: std_logic_vector(8 downto 0):= (others => '0'); signal PWM_OUT: std_logic; signal tvalid: std_logic; signal m_axis_data_tvalid : STD_LOGIC; signal m_axis_data_tdata : STD_LOGIC_VECTOR(7 DOWNTO 0); COMPONENT dds_compiler_0 PORT ( aclk : IN STD_LOGIC; s_axis_phase_tvalid : IN STD_LOGIC; s_axis_phase_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tdata : OUT STD_LOGIC_VECTOR(7 DOWNTO 0) ); END COMPONENT; begin senb <= swt; tvalid <= swt; DIVIDER:process(clk, rst) begin if rst = '1' then cntr <= (others=> '0'); else if (rising_edge(clk)) then cntr <= cntr + 1; end if; end if; end process; clkdiv <= cntr(13); inst_1: dds_compiler_0 port map ( aclk => clk, s_axis_phase_tvalid => tvalid, s_axis_phase_tdata => cntr(20 downto 13), m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tdata => m_axis_data_tdata); PWM_IN <= m_axis_data_tdata(7 downto 0); PWM:process(clkdiv,PWM_IN) begin if rising_edge(clkdiv) then PWM_ACC <= ("0" & PWM_ACC(7 downto 0)) + ("0" & PWM_IN); end if; end process; dataout <= PWM_ACC(8); analogout <= PWM_IN; end Behavioral;
  3. @D@n, Thank you. I will check back through my program and correct them all.
  4. @D@n, As usual, you are a genius. It took a few tries, but I got it. Thanks Royal Here is the code if anyone is interested... P1: process(clk, rst, btn_a, on_a) begin if rst = '1' and btn_a = '0' then on_a <= '0'; elsif rst = '0' and btn_a = '1' then cntra <= (others => '0'); on_a <= '1'; elsif (rising_edge(clk) and on_a = '1') then cntra <= cntra +1; if cntra < 200000000 then on_a <= '1'; else on_a <= '0'; end if; end if; end process;
  5. I have created a soundbox with different sounds connect to different buttons and switches. The switches work fine. High '1' is on, and low '0' is off. I would like my buttons to latch for 3 seconds. I would like to press the button, release it, and have the sound play for 3 seconds. Some call this a one-shot, where a single press latches the bit until unlatched. My code is VHDL in Vivado 2016.4. My board is a BASYS3. I tried using a wait statement, but others have suggested that wait statements do not synthesize. Here is what I have. All help is appreciated. Thanks! period - constance set to 1000ms tempdata - signal std_logic squareout - signal for tone 1 integerout - signal for tone 2 ipcoreout - signal for tone 3 dataout - output from system section of code.... D1: process begin if btn_a = '1' then tempdata <= squareout; wait for 3 * period; elsif btn_b = '1' then tempdata <= integerout; wait for 3 * period; elsif btn_c = '1' then tempdata <= ipcoreout; wait for 3 * period; elsif swt_a = '1' then tempdata <= squareout; wait until swt_a = '0'; elsif swt_b = '1' then tempdata <= integerout; wait until swt_b = '0'; elsif swt_c = '1' then tempdata <= ipcoreout; wait until swt_c = '0'; end if; end process; dataout <= tempdata;
  6. Here is the PMODAMP2_IO XDC code... ## Clock signal set_property PACKAGE_PIN W5 [get_ports {clk}] set_property IOSTANDARD LVCMOS33 [get_ports {clk}] ## Switches set_property PACKAGE_PIN R2 [get_ports {swt}] set_property IOSTANDARD LVCMOS33 [get_ports {swt}] ##Buttons set_property PACKAGE_PIN W19 [get_ports {rst}] set_property IOSTANDARD LVCMOS33 [get_ports {rst}] ##Pmod Header JB ##Sch name = JB1 set_property PACKAGE_PIN A14 [get_ports {dataout}] set_property IOSTANDARD LVCMOS33 [get_ports {dataout}] ##Sch name = JB4 set_property PACKAGE_PIN B16 [get_ports {senb}] set_property IOSTANDARD LVCMOS33 [get_ports {senb}]
  7. @D@n, I got the code working. I needed to go back to my clockdivider (clkdiv) for my Pulse Width Modulator. I makes a series of tones..kinda cool. I need to do some more experimenting and simulating to understand exactly what is happening inside. Here is the code for anyone that is interested along with the IP Core config at the top of this thread. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values -- use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Wave_top is port (clk, swt, rst :in std_logic; dataout, senb: out std_logic ); end Wave_top; architecture Behavioral of Wave_top is signal clkdiv: std_logic; signal cntr: std_logic_vector(31 downto 0); signal PWM_IN: std_logic_vector(10 downto 0); signal PWM_ACC: std_logic_vector(11 downto 0):= (others => '0'); signal PWM_OUT: std_logic; signal tvalid: std_logic; signal m_axis_data_tvalid : STD_LOGIC; signal m_axis_data_tdata : STD_LOGIC_VECTOR(15 DOWNTO 0); COMPONENT dds_compiler_0 PORT ( aclk : IN STD_LOGIC; s_axis_phase_tvalid : IN STD_LOGIC; s_axis_phase_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; begin senb <= swt; tvalid <= swt; DIVIDER:process(clk, rst) begin if rst = '1' then cntr <= (others=> '0'); else if (rising_edge(clk)) then cntr <= cntr + 1; end if; end if; end process; clkdiv <= cntr(13); inst_1: dds_compiler_0 port map ( aclk => clk, s_axis_phase_tvalid => tvalid, s_axis_phase_tdata => cntr(31 downto 24), m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tdata => m_axis_data_tdata); PWM_IN <= m_axis_data_tdata(10 downto 0); PWM:process(clkdiv,PWM_IN) begin if rising_edge(clkdiv) then PWM_ACC <= ("0" & PWM_ACC(10 downto 0)) + ("0" & PWM_IN); end if; end process; dataout <= PWM_ACC(11); end Behavioral;
  8. @D@n, The issue was that I put 's_axis...' and 'm_axis...' in my entity. This caused a conflict because they went nowhere. I just created signals 'm_axis_data_tvalid' and 'm_axis_data_tdata'. It generated a bitstream and ran. It sounds like a rhythmic tapping sound. I will review your initial information on the s_axis_phase_tdata input and do a few more trials. Thanks
  9. @D@n, Out of frustration I tried to generate a bitstream even though the simulation failed. I got an error message "...17 out of 22 logical ports use I/O standard (IOSTANDARD) value 'DEFAULT', instead of a user assigned value." I guess It does not like line 81 s_axis_phase_tvalid => '1', I created a signal tvalid and tied it to my enable switch. The simulation complied and ran ( I forced clk to a 10ns cycle clock, swt to '1', rst to '1' for 5ns then '0'). My simulation ran and I got a dataout signal. But now it will not generate a bitstream. I thought maybe there was a mismatch between the aclk, used with DDS, and clkdiv, used with my PWM output. I changed my PWM to use clk and still no luck. Here is my top_io code for your review. Any ideas are welcomed. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Uncomment the following library declaration if using -- arithmetic functions with Signed or Unsigned values -- use IEEE.NUMERIC_STD.ALL; -- Uncomment the following library declaration if instantiating -- any Xilinx leaf cells in this code. --library UNISIM; --use UNISIM.VComponents.all; entity Wave_top is port (clk, swt, rst :in std_logic; dataout, senb: out std_logic; s_axis_phase_tvalid : IN STD_LOGIC; s_axis_phase_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tdata : INOUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); end Wave_top; architecture Behavioral of Wave_top is signal clkdiv: std_logic; signal cntr: std_logic_vector(31 downto 0); signal PWM_IN: std_logic_vector(10 downto 0); signal PWM_ACC: std_logic_vector(11 downto 0):= (others => '0'); signal PWM_OUT: std_logic; signal tvalid: std_logic; COMPONENT dds_compiler_0 PORT ( aclk : IN STD_LOGIC; s_axis_phase_tvalid : IN STD_LOGIC; s_axis_phase_tdata : IN STD_LOGIC_VECTOR(7 DOWNTO 0); m_axis_data_tvalid : OUT STD_LOGIC; m_axis_data_tdata : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) ); END COMPONENT; begin senb <= swt; tvalid <= swt; DIVIDER:process(clk, rst) begin if rst = '1' then cntr <= (others=> '0'); else if (rising_edge(clk)) then cntr <= cntr + 1; end if; end if; end process; clkdiv <= cntr(13); inst_1: dds_compiler_0 port map ( aclk => clk, s_axis_phase_tvalid => tvalid, s_axis_phase_tdata => cntr(31 downto 24), m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tdata => m_axis_data_tdata); PWM_IN <= m_axis_data_tdata(10 downto 0); PWM:process(clk,PWM_IN) begin if rising_edge(clk) then PWM_ACC <= ("0" & PWM_ACC(10 downto 0)) + ("0" & PWM_IN); end if; end process; dataout <= PWM_ACC(11); end Behavioral;
  10. This is a response question to an earlier thread that I was not able to continue. I did as you suggested. I used the 100MHz clock as aclk. I set s_axis_phase_tvalid to '1', and I used the top bits (Most Significant Bits) of my counter (cntr) for s_axis_phase_tdata. It doesnt show any error, but it will not compile. "ERROR: [VRFC 10-665] expression has 6 elements ; formal s_axis_phase_tdata expects 8" I've tried it with 6, 8 and even all 32-bits and I get the same failure. Code: inst_1: dds_compiler_0 port map ( aclk => clk, s_axis_phase_tvalid => '1', s_axis_phase_tdata => cntr(31 downto 24), -- this is line 82 of Wave_top.vhd m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tdata => m_axis_data_tdata); LOG DATA: Vivado Simulator 2016.4 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto 0fc31941c582466d8f4474edc8fb8bef --debug typical --relax --mt 2 -L xbip_utils_v3_0_7 -L axi_utils_v2_0_3 -L xbip_pipe_v3_0_3 -L xbip_bram18k_v3_0_3 -L mult_gen_v12_0_12 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_3 -L xbip_dsp48_multadd_v3_0_3 -L dds_compiler_v6_0_13 -L xil_defaultlib -L secureip -L xpm --snapshot Wave_top_behav xil_defaultlib.Wave_top -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-665] expression has 6 elements ; formal s_axis_phase_tdata expects 8 [C:/Users/Toshiba-/coregen_sinewave/coregen_sinewave.srcs/sources_1/new/Wave_top.vhd:82] ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit wave_top in library work failed.
  11. I did as you suggested. I used the 100MHz clock as aclk. I set s_axis_phase_tvalid to '1', and I used the top bits (Most Significant Bits) of my counter (cntr) for s_axis_phase_tdata. It doesnt show any error, but it will not compile. "ERROR: [VRFC 10-665] expression has 6 elements ; formal s_axis_phase_tdata expects 8" I've tried it with 6, 8 and even all 32-bits and I get the same failure. Code: inst_1: dds_compiler_0 port map ( aclk => clk, s_axis_phase_tvalid => '1', s_axis_phase_tdata => cntr(31 downto 24), -- this is line 82 of Wave_top.vhd m_axis_data_tvalid => m_axis_data_tvalid, m_axis_data_tdata => m_axis_data_tdata); LOG DATA: Vivado Simulator 2016.4 Copyright 1986-1999, 2001-2016 Xilinx, Inc. All Rights Reserved. Running: C:/Xilinx/Vivado/2016.4/bin/unwrapped/win64.o/xelab.exe -wto 0fc31941c582466d8f4474edc8fb8bef --debug typical --relax --mt 2 -L xbip_utils_v3_0_7 -L axi_utils_v2_0_3 -L xbip_pipe_v3_0_3 -L xbip_bram18k_v3_0_3 -L mult_gen_v12_0_12 -L xbip_dsp48_wrapper_v3_0_4 -L xbip_dsp48_addsub_v3_0_3 -L xbip_dsp48_multadd_v3_0_3 -L dds_compiler_v6_0_13 -L xil_defaultlib -L secureip -L xpm --snapshot Wave_top_behav xil_defaultlib.Wave_top -log elaborate.log Using 2 slave threads. Starting static elaboration ERROR: [VRFC 10-665] expression has 6 elements ; formal s_axis_phase_tdata expects 8 [C:/Users/Toshiba-/coregen_sinewave/coregen_sinewave.srcs/sources_1/new/Wave_top.vhd:82] ERROR: [XSIM 43-3321] Static elaboration of top level VHDL design unit wave_top in library work failed.
  12. I am trying to determine if and how a Vivado IP Core can be used to create and audible tone. I have been reviewing the DSS Compiler 6.0 product guide and simulation tutorial ug937. I have configured it as shown in the attached image. I understand the sine wave output should be bits (10 downto 0) of "m_axis_data_tdata". It is asking for s_axis_phase_tvalid, s_axis_phase_tdata for input. I cannot seem to get a clear understanding of what these are. Can someone explain in layman's terms? I also created a clock divider to drop aclk down to 12kHz as an attempt the get my sine wave into the audible range. I get no output on the board or in the simulator. Ideas???
  13. Thanks again! I will review your info,... and probably be back with more questions. Have a GREAT DAY!
  14. BINGO! That was it! I'm a little embarrassed that I read that so wrong! Thank you! Next question...Can this also be used for integer values or do I need a std_logic_vector?
  15. I am getting 3.3v across JB3:B15 and 1.62v across JB1:A14