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  1. Thank you for your help! I'm using Nexys4 DDR, and the processor is a simple CPU designed by myself. Block design diagram is here: wrapper file is here: xdc file is here:
  2. Hello, I am using Vivado 2017.3, and creating a block design. In this design, I added a AXI Uartlite module, like this: There are two external interfaces: usb_uart_rxd and usb_uart_txd. After I add constraints and run implementation, there are two critical warnings: What is the reason for this? And what should I do? Thanks.
  3. Thank you for your reply! I will first check the blog and projects you gave. Waiting for your new blog Shaw
  4. Hello, I am using Nexys4 DDR and Vivado2017.3(Windows). I want to store some data(instructions) in the qspi flash, and when the board starts, I want to load these data into bram(in the FPGA). I am designing such a program in assembly language(MIPS). I want to know how I need to write this program. Just need to use simple load instructions just like load data from bram? And then, how does the qspi flash controller(AXI IP) convert the load instruction into a spi flash command? I am a newbie of FPGA, I don't know if my description is clear enough. Finally, thanks for your help.
  5. Hello, I am using Xilinx Vivado 2014.3.1 I'd like to use SRAM to DDR Component in my project. First of all, I want to test the component, the top module is at the bottom. Just like the top module, I write the ddr three times at three address, and read them after some cycles. However, the read data in board is wrong and random. The result is here: ram_dq_i ram_dq_o 1st write 1234 0000 2nd write 5678 0000 3rd write 9abc 0000 1st read 1111 1234 2nd read 2222 5678 3rd read 3333 9abc However, the read data(ram_dq_o) may be change with cycles. Could someone help me with this issue? Thanks test_ddr.v
  6. Thank you for the explanation. This indeed helps a lot as it brings my thinking on the right track. Shaw
  7. Thank you Dan for fast response. I'm sorry about my unclear description. My project has two clock, the first one is system clock(100MHZ), the second is DDR clock(200MHZ). The clock function is used to generate the two clock. And then, I used your suggestion and disabled the cen line between the memory commands. Fortunately, when I saw the 7-segment, the result is right. Now, I'd like to use SRAM to DDR Component in another bigger project. At that, I want to kown the reason why I should disable the cen line. Thanks, Shaw
  8. Hello, I am using Xilinx Vivado 2014.3.1 I'd like to use SRAM to DDR Component in my project. But I am newbie in VHDL, so I could just use the methods from this post. And finally, I had made a testbench which could write data into DDR memory and read data from the DDR. It's successful in Synthesis, Implementation and Generate bitstream. There are no critical wornings and errors. I want to use 7-segment to display the data that read from the DDR, however, it didn't work. This is my top module. Could someone help me with this issue? Thanks, Shaw test_ddr.v