I'm currently working on a project and i need to use differential signaling.
I'm using Arty development platform (designed around the Artix-7™ FPGA) and I have some problems in generating the two differential signals (P and N). I used an oscilloscope to check the signal that I want to be sent (MDO) by configuring it as a single ended signal and it is correct. But when I use OBUFDS the two differential signals are logic low all time. I put the verilog code below and the .xdc file configuration.
Thank you very much! Have a good day!
.IOSTANDARD("TMDS_33"), // Specify the output I/O standard
.SLEW("FAST") // Specify the output slew rate
) OBUFDS_inst (
.O(ME_DIFF_P), // Diff_p output
.OB(ME_DIFF_N), // Diff_n output
.I(MDO) // Buffer input
# .xdc file
set_property PACKAGE_PIN U12 [get_ports ME_DIFF_P]
set_property PACKAGE_PIN V12 [get_ports ME_DIFF_N]
set_property IOSTANDARD TMDS_33 [get_ports ME_DIFF_P]
set_property IOSTANDARD TMDS_33 [get_ports ME_DIFF_N]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]