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  1. What I'v done to solve the problem is detailed in the link below. Thanks jpeyron !
  2. 1-2) I made a lot of test (using others signals) and I'm configuring the ARTY with that configuration. There are not any errors related to the XDC file. 3-4) I'm using the first and the second pins from pmod port JC and they are side-by-side. I'm making test for about two days and those two signals are the only one that are causing me problems. Thank you, Andrei
  3. Hello! I'm currently working on a project and i need to use differential signaling. I'm using Arty development platform (designed around the Artix-7™ FPGA) and I have some problems in generating the two differential signals (P and N). I used an oscilloscope to check the signal that I want to be sent (MDO) by configuring it as a single ended signal and it is correct. But when I use OBUFDS the two differential signals are logic low all time. I put the verilog code below and the .xdc file configuration. Thank you very much! Have a good day! OBUFDS #( .IOSTANDARD("TMDS_33"), // Specify the output I/O standard .SLEW("FAST") // Specify the output slew rate ) OBUFDS_inst ( .O(ME_DIFF_P), // Diff_p output .OB(ME_DIFF_N), // Diff_n output .I(MDO) // Buffer input ); # .xdc file set_property PACKAGE_PIN U12 [get_ports ME_DIFF_P] set_property PACKAGE_PIN V12 [get_ports ME_DIFF_N] set_property IOSTANDARD TMDS_33 [get_ports ME_DIFF_P] set_property IOSTANDARD TMDS_33 [get_ports ME_DIFF_N] set_property CONFIG_VOLTAGE 3.3 [current_design] set_property CFGBVS VCCO [current_design] set_switching_activity -deassert_resets