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  1. Thanks Arthur that explains it. Jacob
  2. I'm trying to get the Arty Z7-20 board to simply print "hello world" to the SDK terminal. I have the board files installed from GitHub. I made a vivado project with the Zynq PS and a few random IPs. The PS is configured to use UART0 (mio pins 14/15). When I run the hello world example in the SDK, I don't get anything on the COM port and the TX/RX LEDs don't light up. There are 2 COM ports that SDK detects (3 and 4). If I try to connect to 3 it says it's already connected. I'm assuming this is the because it uses COM3 for downloading the program. So I connect to COM4 @ 115200. Any ideas on how to debug this issue? Thanks EDIT: I was able to get it working---the issue was resolved by deleting and regenerating the BSP in SDK. I've never had to do this before as SDK has done all of the regenerating automatically. Can someone explain a bit why/when it is necessary to regenerate the BSP?
  3. Can you explain more please? What do I need to do exactly? More info: after programming the device from SDK, /dev/ttyUSB0 disappears and can't be connected to. Thanks, Jacob
  4. Hi, I have a design running on a Zybo (basically the Hello World example project) and am trying to connect to the device post-programming over the serial port. The device programs fine (I installed the Digilent USB drivers) but I can't figure out how to connect to view the incoming serial port data. I have tried connecting both from Xilinx SDK using the terminal and also with mini/picocom. SDK says "nothing found at port: ttyUSBx" for both USB0 and USB1. Picocom cannot detect anything on ttyUSB0. It connects to USB1 but nothing is displayed. Which should I be connecting to, USB0 or USB1? Thanks, Jacob
  5. Thanks!! For the benefit of anyone else having issues with this: Adding the design.txt as a simulation source fixed it. I also had to make sure I was reading the correct address pin. module tb(); localparam T=10; reg clk; always begin clk = 1'b1; #(T/2); clk = 1'b0; #(T/2); end wire enable; wire ready; wire [15:0] xadc_raw_out; wire [11:0] data; assign data = xadc_raw_out[15:4] + 12'b1000_0000_0000; // convert from signed to unsigned wire [4:0] ch; reg [6:0] addr = 6'h16; //xadc instantiation connect the eoc_out .den_in to get continuous conversion xadc_wiz_0 xadc ( .daddr_in(addr), // Address bus for the dynamic reconfiguration port .dclk_in(clk), // Clock input for the dynamic reconfiguration port .den_in(enable), // Enable Signal for the dynamic reconfiguration port .di_in(16'd0), // Input data bus for the dynamic reconfiguration port .dwe_in(1'd0), // Write Enable for the dynamic reconfiguration port .reset_in(1'd0), // Reset signal for the System Monitor control logic .vauxp6(), // Auxiliary channel 6 .vauxn6(), .busy_out(), // ADC Busy signal .channel_out(ch), // Channel Selection Outputs .do_out(xadc_raw_out), // Output data bus for dynamic reconfiguration port .drdy_out(ready), // Data ready signal for the dynamic reconfiguration port .eoc_out(enable), // End of Conversion Signal .eos_out(), // End of Sequence Signal .alarm_out() // OR'ed output of all the Alarms ); endmodule
  6. I am trying to create a simple design that reads an analog waveform from the XADC. Can some explain how exactly to do this? I'm a bit confused about how the interface works. I've read through the XADC and XADC wizard documents from Xilinx. I set up my project with the XADC wizard and created a test bench shown below. When I run the sim, it says "Warning: The analog data file design.txt for XADC instance tb.xadc.inst was not found." I configured the XADC wizard to generate a sine wave for sim (also see below for the XADC settings that the wizard generated).The Xilinx XADC wizard document shows the analog waveform being displayed in the sim, but doesn't explain how to set that up (https://www.xilinx.com/support/documentation/ip_documentation/xadc_wiz/v3_0/pg091-xadc-wiz.pdf page 44). The simulation shows the XADC digital output always being 0. I'm not sure if it's a problem with the design.txt or the way I'm interfacing with the DRP port. I read on another forum that the enable port needs to be periodically enabled, but that doesn't really make much sense to me. My understanding is that the DRP port is for writing to the XADC internal registers that change its configuration. Is that correct? How do I need to interact with the DRP port in order for it to sample data? Clearly I'm missing something simple here. Thanks! module tb(); localparam T=10; reg clk; always begin clk = 1'b1; #(T/2); clk = 1'b0; #(T/2); end reg enable; always begin enable = 1'b1; #T; enable = 1'b0; #(15*T); end wire data_ready; wire [15:0] xadc_data_out; reg [11:0] xadc_data; wire eoc; xadc_wiz_0 xadc ( .daddr_in(), .den_in(enable), .dwe_in(), .di_in(), .busy_out(), .drdy_out(data_ready), .do_out(xadc_data_out), .dclk_in(clk), .reset_in(rst), .vp_in(), .vn_in(), .vauxp6(), .vauxn6(), .channel_out(), .eoc_out(eoc), .alarm_out(), .eos_out() ); always @(posedge data_ready) begin xadc_data <= xadc_data_out[11:0]; end endmodule XADC #( .INIT_40(16'h0416), // config reg 0 .INIT_41(16'h31AF), // config reg 1 .INIT_42(16'h0400), // config reg 2 .INIT_48(16'h0100), // Sequencer channel selection .INIT_49(16'h0000), // Sequencer channel selection .INIT_4A(16'h0000), // Sequencer Average selection .INIT_4B(16'h0000), // Sequencer Average selection .INIT_4C(16'h0000), // Sequencer Bipolar selection .INIT_4D(16'h0000), // Sequencer Bipolar selection .INIT_4E(16'h0000), // Sequencer Acq time selection .INIT_4F(16'h0000), // Sequencer Acq time selection .INIT_50(16'hB5ED), // Temp alarm trigger .INIT_51(16'h57E4), // Vccint upper alarm limit .INIT_52(16'hA147), // Vccaux upper alarm limit .INIT_53(16'hCA33), // Temp alarm OT upper .INIT_54(16'hA93A), // Temp alarm reset .INIT_55(16'h52C6), // Vccint lower alarm limit .INIT_56(16'h9555), // Vccaux lower alarm limit .INIT_57(16'hAE4E), // Temp alarm OT reset .INIT_58(16'h5999), // VCCBRAM upper alarm limit .INIT_5C(16'h5111), // VCCBRAM lower alarm limit .INIT_59(16'h5555), // VCCPINT upper alarm limit .INIT_5D(16'h5111), // VCCPINT lower alarm limit .INIT_5A(16'h9999), // VCCPAUX upper alarm limit .INIT_5E(16'h91EB), // VCCPAUX lower alarm limit .INIT_5B(16'h6AAA), // VCCDdro upper alarm limit .INIT_5F(16'h6666), // VCCDdro lower alarm limit .SIM_DEVICE("ZYNQ"), .SIM_MONITOR_FILE("design.txt") )
  7. Well the fix on this was embarrassingly simple... my USB cable was the problem. The power pins were working but not so for the data. Thanks anyway!
  8. I am having issues connecting to the Zybo board. I'm following the "Getting started with the Zybo" tutorial: https://reference.digilentinc.com/learn/programmable-logic/tutorials/zybo-getting-started-with-zynq/start When I try to program the device, I get the error "Could not find FPGA device on the board for connection 'Local'". The board is plugged in and I have PGOOD and DONE LEDs illuminated. I've tried installing and reinstalling the cable drivers. They seem to install successfully. Log file attached. Ideas on how to debug this? Thanks! install.log