jacobfeder

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jacobfeder last won the day on July 23 2018

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  1. Not sure what's going wrong with yours. Below is the code I used. Hope it helps. wire xadc_conv_done; wire [15:0] xadc_data_wire; reg [15:0] xadc_data; always @(posedge clk) begin if (!m_axis_aresetn) begin xadc_data <= 0; end else begin if (xadc_conv_done) begin xadc_data <= xadc_data_wire; end end end xadc_wiz_0 adc ( .m_axis_tvalid(xadc_conv_done), // output wire m_axis_tvalid .m_axis_tready(1), // input wire m_axis_tready .m_axis_tdata(xadc_data_wire), // output wire [15 : 0] m_axis_tdata .m_axis_tid(), // output wire [4 : 0] m_axis_tid .m_axis_aclk(clk), // input wire m_axis_aclk .s_axis_aclk(clk), // input wire s_axis_aclk .m_axis_resetn(m_axis_aresetn), // input wire m_axis_resetn .vp_in(0), // input wire vp_in .vn_in(0), // input wire vn_in .vauxp6(analog_in_p), // input wire vauxp6 .vauxn6(analog_in_n), // input wire vauxn6 .channel_out(), // output wire [4 : 0] channel_out .eoc_out(), // output wire eoc_out .alarm_out(), // output wire alarm_out .eos_out(), // output wire eos_out .busy_out() // output wire busy_out );
  2. Firstly, start off simple and do a single channel measurement instead of channel sequencing. Second, your DCLK and RESET signals in the simulation seem to not be doing what they should be... I think you need to create a verilog/VHDL test bench.
  3. Can you attach files or show how you initialized
  4. Why do you have 2 design.txt? Can we see the rest of the hierarchy? It's been awhile since I did this but I think you need to initialize it somehow.
  5. In the block diagram view use the XADC wizard it gives an option to create a design.txt which you can use or modify
  6. Thanks!! This did it (firmware files were already present in my host machine's /lib/firmware). I also had to enable wpa-supplicant and wpa-supplicant-cli in the rootfs in order to connect to the wireless network. Thanks again. Cheers, Jacob
  7. Actually this did fix the USB bus .... I made a mistake including the file into my project. If you add those lines to system-user.dtsi the USB system works. However, now I am having a problem getting the wifi driver working. The device is a Realtek RTL8188CUS. I included the following drivers with petalinux-config -c kernel: - Networking support -> Wireless -> cfg80211 - Networking support -> Wireless -> Generic IEEE 802.11 Networking Stack - Device Drivers -> Network device support -> Wireless LAN -> Realtek tflwifi family of devices -> Realtek RTL8192CU/RTL8188CU USB Wireless Network Adapter - Device Drivers -> Network device support -> Wireless LAN -> RTL8723AU/RTL8188[CR]U/RTL819[12]CU (mac80211) support - Device Drivers -> Network device support -> Wireless LAN -> Include support for untested Realtek 8xxx USB devices (EXPERIMENTAL) After booting lsusb reports: Bus 001 Device 002: ID 7392:7811 Which is the device. However, the driver doesn't appear to be loading properly: root@default_linux:~# dmesg | grep usb usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb usbcore: registered new interface driver rtl8192cu usbcore: registered new interface driver rtl8xxxu usbcore: registered new interface driver usb-storage chipidea-usb2 e0002000.usb: e0002000.usb supply vbus not found, using dummy regulator usbcore: registered new interface driver usbhid usbhid: USB HID core driver usb 1-1: new high-speed USB device number 2 using ci_hdrc rtl_usb: rx_max_size 15360, rx_urb_num 8, in_ep 1 usb 1-1: Direct firmware load for rtlwifi/rtl8192cufw_TMSC.bin failed with error -2 usb 1-1: Direct firmware load for rtlwifi/rtl8192cufw.bin failed with error -2 If I don't include - Device Drivers -> Network device support -> Wireless LAN -> Include support for untested Realtek 8xxx USB devices (EXPERIMENTAL) I get: root@default_linux:~# dmesg | grep usb usbcore: registered new interface driver usbfs usbcore: registered new interface driver hub usbcore: registered new device driver usb usbcore: registered new interface driver rtl8xxxu usbcore: registered new interface driver usb-storage chipidea-usb2 e0002000.usb: e0002000.usb supply vbus not found, using dummy regulator usbcore: registered new interface driver usbhid usbhid: USB HID core driver usb 1-1: new high-speed USB device number 2 using ci_hdrc Any ideas? Thanks, Jacob
  8. Ok, I gave this a try and still wasn't able to get it working. I tried adding the following to "project-spec/meta-user/recipes-bsp/device-tree/files/system-user.dtsi" which were present in the github petalinux project that you linked. /include/ "system-conf.dtsi" / { usb_phy0: usb_phy@0 { compatible = "ulpi-phy"; #phy-cells = <0>; reg = <0xe0002000 0x1000>; view-port = <0x0170>; drv-vbus; }; }; &usb0 { usb-phy = <&usb_phy0>; dr_mode = "host"; /delete-property/ usb-reset; }; I checked the menuconfig files but there didn't seem to be any significant differences relating to USB although there were many changes (just due to using different kernel versions). Any other ideas? I'm sort of at a loss for how to debug this. Thanks, Jacob
  9. Thanks for the reply. USB flash drives also do not work. My intuition is that the problem has to do with Petalinux trying to make it function as device / host / OTG rather than host only. I have tried disabling the OTG / device drivers in the kernel config but that didn't do it. I will compare the github project to my own and see if I can find any significant differences. Thanks again! Jacob
  10. jacobfeder

    Arty Z7 USB

    Hi, I'm trying to use a USB wifi dongle on the Arty Z7 (Z020). I followed instructions here: http://www.wiki.xilinx.com/Zynq+Linux+USB+Device+Driver as well as trying many other driver combinations (I also tried enabling host mode only). Still, I'm not able to detect any connected USB devices (nothing happens in lsusb or dmesg when devices are connected / disconnected). In U-boot I am able to detect usb devices using "usb start" and "usb info". Any ideas? Thanks
  11. Thanks Arthur that explains it. Jacob
  12. I'm trying to get the Arty Z7-20 board to simply print "hello world" to the SDK terminal. I have the board files installed from GitHub. I made a vivado project with the Zynq PS and a few random IPs. The PS is configured to use UART0 (mio pins 14/15). When I run the hello world example in the SDK, I don't get anything on the COM port and the TX/RX LEDs don't light up. There are 2 COM ports that SDK detects (3 and 4). If I try to connect to 3 it says it's already connected. I'm assuming this is the because it uses COM3 for downloading the program. So I connect to COM4 @ 115200. Any ideas on how to debug this issue? Thanks EDIT: I was able to get it working---the issue was resolved by deleting and regenerating the BSP in SDK. I've never had to do this before as SDK has done all of the regenerating automatically. Can someone explain a bit why/when it is necessary to regenerate the BSP?
  13. Can you explain more please? What do I need to do exactly? More info: after programming the device from SDK, /dev/ttyUSB0 disappears and can't be connected to. Thanks, Jacob
  14. Hi, I have a design running on a Zybo (basically the Hello World example project) and am trying to connect to the device post-programming over the serial port. The device programs fine (I installed the Digilent USB drivers) but I can't figure out how to connect to view the incoming serial port data. I have tried connecting both from Xilinx SDK using the terminal and also with mini/picocom. SDK says "nothing found at port: ttyUSBx" for both USB0 and USB1. Picocom cannot detect anything on ttyUSB0. It connects to USB1 but nothing is displayed. Which should I be connecting to, USB0 or USB1? Thanks, Jacob
  15. Thanks!! For the benefit of anyone else having issues with this: Adding the design.txt as a simulation source fixed it. I also had to make sure I was reading the correct address pin. module tb(); localparam T=10; reg clk; always begin clk = 1'b1; #(T/2); clk = 1'b0; #(T/2); end wire enable; wire ready; wire [15:0] xadc_raw_out; wire [11:0] data; assign data = xadc_raw_out[15:4] + 12'b1000_0000_0000; // convert from signed to unsigned wire [4:0] ch; reg [6:0] addr = 6'h16; //xadc instantiation connect the eoc_out .den_in to get continuous conversion xadc_wiz_0 xadc ( .daddr_in(addr), // Address bus for the dynamic reconfiguration port .dclk_in(clk), // Clock input for the dynamic reconfiguration port .den_in(enable), // Enable Signal for the dynamic reconfiguration port .di_in(16'd0), // Input data bus for the dynamic reconfiguration port .dwe_in(1'd0), // Write Enable for the dynamic reconfiguration port .reset_in(1'd0), // Reset signal for the System Monitor control logic .vauxp6(), // Auxiliary channel 6 .vauxn6(), .busy_out(), // ADC Busy signal .channel_out(ch), // Channel Selection Outputs .do_out(xadc_raw_out), // Output data bus for dynamic reconfiguration port .drdy_out(ready), // Data ready signal for the dynamic reconfiguration port .eoc_out(enable), // End of Conversion Signal .eos_out(), // End of Sequence Signal .alarm_out() // OR'ed output of all the Alarms ); endmodule