toshas got a reaction from daryon in Unable to grab PCIe ref_clk for the axi_pcie in ZC706 board !
Check page 45 in https://www.xilinx.com/support/documentation/boards_and_kits/zc706/ug954-zc706-eval-board-xc7z045-ap-soc.pdf
N8 MGTREFCLK0P_112 PCIE_CLK_QO_P A13 (1)
N7 MGTREFCLK0N_112 PCIE_CLK_QO_N A14 (1)
So just create clock input pins in your block diagram with any names.
After that define constraints in xdc file which connects your clk names to N7/N8 pins.