toshas

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Everything posted by toshas

  1. Hi! Glad to hear it! Could you share code with community, so anyone could reuse it ?
  2. Hi, Here are two points which should be taken into account : 1) Reset time - strap's are applied after power on. FPGA configuration time can be much more. In this case special reset sequence after boot up is needed. 2) Internal pull-ups are weak. They can be not sufficient for set correct logic level. As per TI datasheet 2.2k pullup is required. https://forums.xilinx.com/t5/Processor-System-Design/Zynq-7000-Pull-up-down-Resistor-Value-Thread/td-p/939389 https://www.xilinx.com/support/answers/67577.html
  3. Also let's check RMII mode selection. (Table 3-8. Strap Options http://www.ti.com/lit/ds/sllsec6e/sllsec6e.pdf ) External board which I mensioned above has pull-up on RX_DV, Arty by default hasn't it. Did you solder it on board ?
  4. 25MHz is for MII, 50Mhz is for RMII Check RMII specifications and DP83848 datasheet, Table 3-4. Clock Interface http://www.ti.com/lit/ds/sllsec6e/sllsec6e.pdf
  5. I rechecked your diagram, looks like rxd[1] is missing, isn't it ?
  6. I'm sorry it was typo, I mean DP83848. I used external board with PHY like this one https://www.waveshare.com/dp83848-ethernet-board.htm This board has external 50MHz clocking required for RMII. Here is my BD, settings and XDC. design_1.pdf xdc.xdc
  7. Check info above, if it will not help you, I can share working RMII project for Arty board with you (2017.3).
  8. Hi! Which PHY IC you are using ? There are several versions of RMII. MII-to-RMII core is designed according v1.0 specification. DP83848 PHY has RMII v1.2 by default (register 0x17, default value 0x21). So there can be mismatch, and at least Zynq processor is sensitive for that. In such cases you should change it (register 0x17, set value to 0x31), apply this for SDK: FOR PS GEM CORE add XEmacPs_PhyRead(xemacpsp, phy_addr, 0x17, &status); xil_printf("RMII = %x\r\n",status); XEmacPs_PhyWrite(xemacpsp, phy_addr, 0x17, 0x31); XEmacPs_PhyR
  9. I'm pretty sure about it. But right now I'm unable to test it again. XCZU4/5/7 were moved to WebPACK since 2017.4
  10. Zynq Ultrascale+ devices up to XCZU7EV are included into Vivado WebPACK Tool. page 9 of https://www.xilinx.com/support/documentation/sw_manuals/xilinx2019_2/ug973-vivado-release-notes-install-license.pdf In this case no special license is required, WebPACK Tool is free.
  11. New Digilent board Genesys ZU has even higher price XCZU3EG - $1,149.00 Xilinx ZCU104 (with XCZU7EV) price is $895
  12. Trenz released board with 2 PMOD connectors for Ultra96 https://shop.trenz-electronic.de/en/TEP0006-01-Ultra96-Pmod-Adapter
  13. Yes, but they did it only for several PMOD's. Digilent provides examples based on HDL code or C MCU code for most PMOD's. We are using a lot of Digilent sensors in education process and every year some students prefer to use them with Raspberry PI as system board. So they asking about python examples.
  14. Hi! There is a PMOD HAT for Raspberry PI - https://store.digilentinc.com/pmod-hat-adapter-pmod-expansion-for-raspberry-pi/ Actually DesignSpark provide support for very limited set of PMOD's (PmodAD1, PmodHB3, PmodISNS20, PmodMIC3, PmodOLEDrgb and PmodTC1) https://github.com/DesignSparkrs/DesignSpark.Pmod It would be nice to have Python examples for other PMOD's too (like TMP3, HYGRO, IMU, NAV and so on). Thanks!
  15. Hi! Here is a small anouncement https://forums.ni.com/t5/NI-Blog/LabVIEW-Community-Edition/ba-p/3970512 New version of LINX will be released in May 2020 and beta is available now through Software Technology Preview website.
  16. Hi! Is it possible to unlock LINX forums https://www.labviewmakerhub.com/forums/index.php ? Right now newly registered users unable to post anything there. So LINX disscussion would be continue on appropriate place.
  17. Hi! Since Digilent has no MPSOC boards right now. It would be nice to have HAT for Ultra96 board with several PMOD ports (4 or even more). (Similar HAT was already released for RaspberryPi.) What do you think about it ? I found almost the same request on another forum https://discuss.96boards.org/t/pmod-interface-solution/6732/3 Someone want to order up to 100 boards.
  18. Hi! Is there any plans to upload sources of liblinxdevice .so on github? Raspbian Stretch has 1-wire support. It would be nice to add this interface to LINX. I can see only "dummy" project LinxDeviceLibWin (VS project for dummy liblinxdevice.dll) Thanks a lot!
  19. Hi! Check packets with Wireshark. It is good ethernet sniffer tools. You will be able to see what is actually inside your tcp packets.
  20. Hi! Check page 45 in https://www.xilinx.com/support/documentation/boards_and_kits/zc706/ug954-zc706-eval-board-xc7z045-ap-soc.pdf It stated: N8 MGTREFCLK0P_112 PCIE_CLK_QO_P A13 (1) N7 MGTREFCLK0N_112 PCIE_CLK_QO_N A14 (1) So just create clock input pins in your block diagram with any names. After that define constraints in xdc file which connects your clk names to N7/N8 pins.
  21. toshas

    LINX VISA MEMACC ?

    Sure! I'm sorry because of incomplete description. I would like to allocate some amount of memory inside of LINX. Then send offset address to external linux application. And then send some amount of data from external application.
  22. toshas

    LINX VISA MEMACC ?

    Hi! MEMACC is a special VISA resource for memory allocation. http://zone.ni.com/reference/en-XX/help/370131S-01/ni-visa/memacc_resource/ Is it woking on LINX ? I can't find it. Is there any other available method for memory allocation in LINX ? Will "chroot system" be a problem for this task ? I found some info here (some kind of MMap API): https://lavag.org/topic/18725-communicating-between-windows-virtual-memory-and-myrio-fpga/ https://lvs-tools.co.uk/software/utilities-labview-library/ Is it right direction ? P.S. I am linux user not a pro, so answers with expla
  23. Hi! Could you confirm that FMC-CE will work with Xilinx boards which has only 1.8V Vadj on FMC slot ? Thanks!