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  1. Hi! Glad to hear it! Could you share code with community, so anyone could reuse it ?
  2. Hi, Here are two points which should be taken into account : 1) Reset time - strap's are applied after power on. FPGA configuration time can be much more. In this case special reset sequence after boot up is needed. 2) Internal pull-ups are weak. They can be not sufficient for set correct logic level. As per TI datasheet 2.2k pullup is required.
  3. Also let's check RMII mode selection. (Table 3-8. Strap Options ) External board which I mensioned above has pull-up on RX_DV, Arty by default hasn't it. Did you solder it on board ?
  4. 25MHz is for MII, 50Mhz is for RMII Check RMII specifications and DP83848 datasheet, Table 3-4. Clock Interface
  5. I rechecked your diagram, looks like rxd[1] is missing, isn't it ?
  6. I'm sorry it was typo, I mean DP83848. I used external board with PHY like this one This board has external 50MHz clocking required for RMII. Here is my BD, settings and XDC. design_1.pdf xdc.xdc
  7. Check info above, if it will not help you, I can share working RMII project for Arty board with you (2017.3).
  8. Hi! Which PHY IC you are using ? There are several versions of RMII. MII-to-RMII core is designed according v1.0 specification. DP83848 PHY has RMII v1.2 by default (register 0x17, default value 0x21). So there can be mismatch, and at least Zynq processor is sensitive for that. In such cases you should change it (register 0x17, set value to 0x31), apply this for SDK: FOR PS GEM CORE add XEmacPs_PhyRead(xemacpsp, phy_addr, 0x17, &status); xil_printf("RMII = %x\r\n",status); XEmacPs_PhyWrite(xemacpsp, phy_addr, 0x17, 0x31); XEmacPs_PhyRead(xemacpsp, phy_addr, 0x17, &status); xil_printf("RMII = %x\r\n",status); after if (conv_present) { XEmacPs_PhyWrite(xemacpsp, convphyaddr, XEMACPS_GMII2RGMII_REG_NUM, convspeeddupsetting); } in file xemacpsif_physpeed.c (*\*_prj.sdk\*_bsp\ps7_cortexa9_0\libsrc\lwip141_v1_9\src\contrib\ports\xilinx\netif) in function u32_t phy_setup (XEmacPs *xemacpsp, u32_t phy_addr) (used when speed is fixed), when speed is auto get_IEEE_phy_speed(XEmacPs *xemacpsp, u32_t phy_addr) function is used (it seems like that) FOR LITE CORE add XEmacLite_PhyRead(xemaclitep, phy_addr, 0x17, &control); xil_printf("RMII = %x\r\n",control); XEmacLite_PhyWrite(xemaclitep, phy_addr, 0x17, 0x31); XEmacLite_PhyRead(xemaclitep, phy_addr, 0x17, &control); xil_printf("RMII = %x\r\n",control); after u32 phy_addr = detect_phy_emaclite(xemaclitep); in file xemacliteif.c (*\*_prj.sdk\*_bsp\ps7_cortexa9_0\libsrc\lwip141_v1_9\src\contrib\ports\xilinx\netif) in function unsigned get_IEEE_phy_speed_emaclite(XEmacLite *xemaclitep) (when speed is auto), when fixed configure_IEEE_phy_speed_emaclite function is used. p.s. It was tested on Vivado v2017.3 , Zybo board and external DP83848 PHY.
  9. I'm pretty sure about it. But right now I'm unable to test it again. XCZU4/5/7 were moved to WebPACK since 2017.4
  10. Zynq Ultrascale+ devices up to XCZU7EV are included into Vivado WebPACK Tool. page 9 of In this case no special license is required, WebPACK Tool is free.
  11. New Digilent board Genesys ZU has even higher price XCZU3EG - $1,149.00 Xilinx ZCU104 (with XCZU7EV) price is $895
  12. Trenz released board with 2 PMOD connectors for Ultra96
  13. Yes, but they did it only for several PMOD's. Digilent provides examples based on HDL code or C MCU code for most PMOD's. We are using a lot of Digilent sensors in education process and every year some students prefer to use them with Raspberry PI as system board. So they asking about python examples.
  14. Hi! There is a PMOD HAT for Raspberry PI - Actually DesignSpark provide support for very limited set of PMOD's (PmodAD1, PmodHB3, PmodISNS20, PmodMIC3, PmodOLEDrgb and PmodTC1) It would be nice to have Python examples for other PMOD's too (like TMP3, HYGRO, IMU, NAV and so on). Thanks!
  15. Hi! Here is a small anouncement New version of LINX will be released in May 2020 and beta is available now through Software Technology Preview website.