  # Yannick

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## Everything posted by Yannick

1. @D@n I am totally agree with your explanations and the simulation shows exactly what I was expecting, of course. Yes, I believed that it was between -1 and 1 but when I read this (picture 1), I made the conclusion of the [-1/2 ; 1/2] range. I'm probably totally wrong (probably a misunderstanding as english is not my native language as you probably guessed ^^). My coefficients have 16 bits and the result of the multiplication as well, however the output width calculated by the FIR is 36 bits (picture 2) and finally, 40 bits as it is shown in the previous pictures of simulations (as it has to be a multiple of 8 if I well understood). My main question was how to interpret this 40 bits vector, so if I follow your reasoning, in the first case where the signal is filtered, the amplitude of the output near DC is 0 ? Besides, why do I have negative values with this 40bits vector ?
2. @D@n, Okay, I understand some points ! But, I'm not sure to have well understood how to know the amplitude of the filter output. In the both cases here, I have 2 sine wave generated by a DDS, in unit circle mode which means, the range is [-0.5 ; 0.5]. Then, the two signals are multiplied. It gives me the signal called "result" with a [0 ; 1] range. Finally, this signal is low pass filtered (cut off frequency of the filter is 100 kHz) and I obtain this value on 40 bits which I don't understand. I don't know how to interpret it. Picture 1 : the 2 sine waves have a frequency of 100 kHz each Picture 2 : the 2 sine waves have a frequency of 20 kHz each
3. Hello, I'm building this filter, generating a .COE file in Matlab, which I use in the FIR compiler IP. Here are two screenshots of the settings. Do you know if the difference between the two pictures, in terms of magnitude, are just a displaying fact or if there is a real amlpification involved by the FIR compiler ? If it's the case, do you know how to fix it to generate the same filter as I designed in Matlab, so without gain ? Kind regards, Yannick
4. @D@n That is what I tried. On the top picture, the output frequency of the DDS (FIR's input) is 1.2 MHz, on the second, 1.35 MHz. I kept the filter's settings mentionned previously. So, normally, in the second picture, the signal should not be the same as on the first picture, right ?
5. Okay, I think I have understood what you mean. In my design, I have wired the valid signal output of the DDS in the valid signal input of the FIR. It should assert correctly the valid signal in entry of the FIR, no ?
6. Hello, I'm currently trying to implement a simple low-pass filter using the FIR Compiler available in the IP catalog. My design is very basic, I've generated a sine wave using the DDS IP : * Configuration Options : Phase generator and SIN COS LUT * System clock : 100 MHz * Mode of operation : Standard * Output frequency : 1.2 MHz * Output width : 8 Bits I want now to apply a low-pass filter and to see how is it going in simulation, using Analog waveform style. To generate the coefficients, I am using Matlab and the filterDesigner. Here are the specifications : * Lowpass, FIR (Equiripple) * Fs : 2.7 MHz * Fpass : 1.3 MHz * Fstop : 1.35 MHz * Apass : 1 dB * Astop :40 dB Then, I generate a .COE file which I use in the FIR compiler. I specify these options : * Filter type : Single rate * Input sampling frequency : 2.7 MHz * Clock frequency : 100 MHz * Coefficient type : signed, on 16 bits * Coefficient structure : Inferred * Input data type : Signed, on 8 bits * Output rounding mode : Full precision The screenshot shows what I obtain and it seems that it is not working very well. Does anybody can explain me what is going on ? Do I make some mistakes when I am setting up the filter ? Thank you very much for your help !
7. Thanks @artvvb ! I took a look on the design challenge and I'm not sure to have well understood. So, for my issue, this is the third part "a real seven segment display controller" that can help me, right ? If so, if we do a comparison, the switches are my bcd0, bcd1, bcd2, bcd3 (each one is 4-bit length like switches). If I well understand, it means that if I want to visualise the number 1932 ("2" in bcd0, "3" in bcd1, "9" in bcd2 and "1" in bcd3) on four different digit display (the four first of the eight) at the same time, I have to use a MUX which will be controlled by a counter ? Which will enable the right Anode to display each number ?
8. Hello ! I'm currently encoutering an issue about how to assign each digit of a number on the seven segment display. For example, if I have the number 1932, how to affect the '2' on the first digit display . The '3' on the second, the '9' on the third, etc... Actually, I have a 4-bit BCD (which functions) and I want to display the decimal number. My output, bcd0, bcd1, bcd2, bcd3 represents the ones, the tens, the hundres and the thousands). I'm decoding each output like that : case bcd0 is when "0000"=> seven_seg<="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; case bcd1 is when "0000"=> seven_seg<="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; case bcd2 is when "0000"=> seven_seg <="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; case bcd3 is when "0000"=> seven_seg <="0000001"; -- '0' when "0001"=> seven_seg<="1001111"; -- '1' when "0010"=> seven_seg<="0010010"; -- '2' when "0011"=> seven_seg<="0000110"; -- '3' when "0100"=> seven_seg<="1001100"; -- '4' when "0101"=> seven_seg<="0100100"; -- '5' when "0110"=> seven_seg<="0100000"; -- '6' when "0111"=> seven_seg<="0001111"; -- '7' when "1000"=> seven_seg<="0000000"; -- '8' when "1001"=> seven_seg<="0000100"; -- '9' when others=> seven_seg<="1111111"; end case; Of course, I know that I have to activate the 4 first anodes (low level). And that I have to assign each bit of "seven_seg" to the good pin on the .XCF file. Thank you very much for help !
9. Hey @D@n ! I had the same opinion, thank you to confirm ! Before implementing an other ADC by plugging it on the PMOD, we finally decided to try to use the internal ADC even if the resolution is 12bit. Maybe it would be enough, we don't know for the moment so let's try ! So I used the XADC wizard and I wrote some VHDL code (definitely not using MicroBlaze ^^ ) to convert a voltage which enter in an auxiliary channel (AD2P/AD2N) on the JXADC, and to display the digital conversion on the LEDs. It seems to work because when I have 0 V none of them light and when I have 1V they all light. But I'm checking if the intermediaries steps well correspond. I was justly wondering how to check efficiently and easily if the conversion is well done (avoiding conversion binary -> decimal and display on 7-segment..). Because playing with the LED's and checking which of them are lighted to try to guess the binary code seem to be a bit archaic ahah. Indeed, some of them are sometimes lighted at half ! So that's where I am for the moment, thank you for asking :). And thank you very much once again for your answers !
10. Hello @D@n ! I'm finally trying to use the JXADC first to acquire a digital signal. I'm currently displaying the channel 3 (AD2N, AD2P) voltage on the LEDs. I use the DRP interface to collect the data in entry of the channel 3 by the DO[15:0] bus. But there's something I don't understand when I read the UG480, page 25. It's written that the 4 LSB are "Note", what does it mean ? When I display the voltage on the LEDs, the first four are always lighted, I don't understand why.
11. Hello @D@n, @artvvb ! Thank you both for your answers ! Actually, I've just started an internship and the goal is to implement a digital lock in amplifier on a board, for an optic detector. Indeed, I'm starting from a photodetector and I want to go through the ADC and then the FPGA to do some on board processing. More precisely, I want to apply the principle of a lock in amplifier which is, in an easy way, to multiply the input signal with a reference (at the same frequency), and then apply a low pass filter to recover a clean signal. So in a first part, to familiarize with the board, I wanted to put a signal from a generator until the ADC, and then light the LED on the Nexys board as I told you (before treating the real signal from the photodector). The second step would be to do the signal processing with the multiplier and the filter. But I was, and I am still, lost on how to plug and set up the ADC on the Pmod port (MicroBlaze? HDL code ? Other way ?) So to aswer to your questions @D@n, yes I want to read from the ADC, to do some on board processing and output the results it in real time. Because, the next step of this digital lock in amplifier is to create an imaging system after collecting the clean signal from the board (photodetector -> ADC -> FPGA -> (image processing) ). Besides, you talked about RPi board. I did not choose the board. Actually, my tutor provided me this Nexys 4 DDR and the Analog Device's ADC (This is a 18-bit resolution ADC, that's why we don't use the ADC from the board) . But I am not obliged to work on this board. I was justly wondering if working on a microcontroller should be easier. What do you think about it ? I am also agree with the debugging point but what do you mean by "add logic into your design" ? Thank you very much once again.
12. Hello ! I'm currently working on a project which consists in designing a digital lock-in amplifier on a FPGA board. For this, I am using a Nexys 4 DDR and an Analog Device's ADC (EVAL AD7984 PMDZ). My first goal is to interface properly the ADC component with the FPGA using a Pmod port. I have some basics knowledge about the use of Vivado so that's why I am asking you about this. I followed the tutorials about "getting started about MicroBlaze" to follow then "using Pmods IP". My question is : When I followed the first tutorial mentionned above, we created a a basic Microblaze block design. Do I have to use all this design or is it possible to do easier ? And, do I have to design it with MicroBlaze or can I just write some VHDL code ? I want in a first part, to give a signal input in the ADC and then, light a LED on the board to confirm that the FPGA is well connected with the ADC. Can you, please, give me a plan to achieve my goal ? I don't ask for a solution, I want to manage it by myself, but just some help to know what are the steps I have to follow. Thank you very much ! Have a good day !