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  1. macellan

    XADC vhdl demo

    I did some more reading during the weekend but somethings are not clear yet ... Sometime ago I've prepared a slow clock counter using clocking wizard and there I've instantiated the clock core as a component which works without any problem. There is no instantiation in the top level file. Instead when I click on "+" sign next to clock ip figure in the sources tab there is an instantiation inside it. But I didn't do anything there. So what is difference here?? p.s ZYBO example design link Thanks in advance! TL_Counter.vhd
  2. macellan

    XADC vhdl demo

    Thank you for the answers both are very helpful. Let me make some more trials and reading then some more questions may appear... macellan
  3. macellan

    XADC vhdl demo

    Hello I'm doing some trials on XADC reference design using ZYBO board and trying to understand how to configure it for another application. However the top level is in Verilog and so far I'm familiar with VHDL. Thus I've tried to convert the top level to VHDL but there is part shown below that I don't understand if it is automatically generated or included by the designer. I'm not familiar with this "dot" type coding and didn't do any similiar so far. If there is a VHDL version it will be very useful for me to understand the concept and also some explanation for the below part will be very nice. Thanks in advance! ============================================================================================= /////////////////////////////////////////////////////////////////// //XADC Instantiation ////////////////////////////////////////////////////////////////// xadc_wiz_0 XLXI_7 ( .daddr_in (Address_in), .dclk_in (clk), .den_in (enable & |sw), .di_in (0), .dwe_in (0), .busy_out (), .vauxp15 (xa_p[2]), .vauxn15 (xa_n[2]), .vauxp14 (xa_p[0]), .vauxn14 (xa_n[0]), .vauxp7 (xa_p[1]), .vauxn7 (xa_n[1]), .vauxp6 (xa_p[3]), .vauxn6 (xa_n[3]), .do_out (data), .vp_in (vp_in), .vn_in (vn_in), .eoc_out (enable), .channel_out (channel_out), .drdy_out (ready) ); =============================================================================================