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  1. Dear @BogdanVanca You are absolutely correctšŸ™ˆ Thank you.
  2. Dear @JColvin I made it work. I don' t have all steps registered right now but the pushbutton decleration part has a missing step. Since we have a reset button we need to specify it. I know that from other example designs. So when adding pushbutton, I only add button1 because button0 is dedicated as a reset button. I' ll try that again and can update this answer, as well. Thank you.
  3. Dear @xc6lx45 thank you for detailed comments. The main purpose of me in here is some curiosity and some necessity. My current system includes an FPGA for main measurement and an arduino for some other controls and measurements (temperature meas., start/stop a pump etc. ). This was more practical for me than a complete vhdl design. So I thought to carry the uController inside the FPGA and build a more compact system. Also this is going to be a new experience. Additionally I was not aware of the speed issue, thank you for that, although speed is not a matter for now. I' ll look at microbl
  4. Hello, I would like to add a memory configuration file to keep the design on flash memory but the link is disabled. Anyone know the reason and how to reactivate it? Thanks in advance
  5. Hello everyone, For a while I am thinking to play with embedded processor of my cmod a7 fpga board and eventually started. I followed the example designs shared on reference designs in digilent pages and also searched the net for other examples. I would like to ask a few questions regarding to some points that I' m having trouble to understand. First of all (maybe easier), I followed this ref example using vivado 2019.1 (SDK, Not Vitis), but it didn' t work for me. For example, I got more options at step 4.11 than given at tutorial. I didn' t think it is an important issue but in th
  6. Dear @[email protected] I' m not complaining about this anymore. Since there is a big time difference between two programming methods, I wanted to be sure if everything is correct or not. In the end, I now taht I need to wait for some seconds tha the board will boot itself. Dear @xc6lx45 The second option looks more useful. Thank you for pointing that out. And your high speed interface design looks not a necessary option for my current needs but thank you for sharing that as well. Kind wishes.
  7. Hi @xc6lx45 Thank you for your suggestion. As in attached picture, I changed the speed 3 to 50 and SPI bus widht 1 to 4. I' m using vivado 2019.1 and these were looking the closest options you mentioned. However, I didn' t observe any difference. I also checked for no erase option since it first erase the loaded design and then load the new one. There is no difference for this option too.
  8. Dear @xc6lx45 and @[email protected] Thank you for your answers. The problem is solved and actually it seems that there was no problem. Because after ~10 seconds the design appeared to be loaded. Since the direct load, through "program device", transfer the design immediately, I was expecting it to happen in a similar fashion. So after checking a few times my design is uploaded successfully. Sorry for taking your time but it was surprising for me that it takes this much time. Kind wishes.
  9. Hello everyone, I would like to keep my design on my Cmod A7 35T board to be able to use it as a stand alone device. Thus I followed the steps given in quad spi programming tutorial. However, I couldn' t make it work. There is no error, warning etc. Everything looks ok but there is no operation. Otherwise when I program through "program device" it works very well. So any idea what is the problem and how to solve it ?? Looking forward to your answers Thanks in advance and best wishes.
  10. Thank you all for the answers. So jtag programmer is not necessary for programming, I got that but do I need anything specific to use ILA? And also cmod stands for what? Any relation with pmod?
  11. Hi everyone, I' m planning to order a breadboardable FPGA board and Cmod 7 Artix 7 board takes my interest for a while. However, I' had difficulty to understand a few points that I want to ask here? For instance I'm not quite sure about the function of JTAG. Do I need a JTAG programmer for uploading the design file or is the USB connection enough for that? Also do I need JTAG programmer for using the Integrated Logic Analyzer as well? A more general question do you recommend me to order a JTAG programmer as well and which one? Additionally, what is Cmod stand for and is there
  12. macellan

    XADC vhdl demo

    I did some more reading during the weekend but somethings are not clear yet ... Sometime ago I've prepared a slow clock counter using clocking wizard and there I've instantiated the clock core as a component which works without any problem. There is no instantiation in the top level file. Instead when I click on "+" sign next to clock ip figure in the sources tab there is an instantiation inside it. But I didn't do anything there. So what is difference here?? p.s ZYBO example design link Thanks in advance! TL_Counter.vhd
  13. macellan

    XADC vhdl demo

    Thank you for the answers both are very helpful. Let me make some more trials and reading then some more questions may appear... macellan
  14. macellan

    XADC vhdl demo

    Hello I'm doing some trials on XADC reference design using ZYBO board and trying to understand how to configure it for another application. However the top level is in Verilog and so far I'm familiar with VHDL. Thus I've tried to convert the top level to VHDL but there is part shown below that I don't understand if it is automatically generated or included by the designer. I'm not familiar with this "dot" type coding and didn't do any similiar so far. If there is a VHDL version it will be very useful for me to understand the concept and also some explanation for the below part will