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  1. One of the Pmod DA4 octal DAC boards we are using in our prototype stopped working. Basically no outputs. I replaced the failed board with another board and everything is all good again. It could have been static, or mishandling during debug so I am not to worried until we have another fail. But if anyone has any suggestions to help investigate, or have seen this before, any feedback would be appreciated. This is a entirely an off the shelf development prototype connected with cables, wires, and hand built connectors boards to verify functionality before spinning custom boards.
  2. I am interested in learning the results.
  3. Mode 2 as described in the AD5628 spec. I am 100% sure if you change to mode 2 it will work for you too. And I would not be surprised if you increase the SCLK to 50MHz with MODE 3 you will have problems. Thanks again for the help
  4. The FPGA CLK is 100MHz not the SPI SCLK to the DAC. The DAC will not operate reliably at an SCLK of 100MHz, especially in Mode 3.
  5. What SCLK rate are you using with the Microblaze? Do you see how that violates the Data sheet spec for the AD5628 and will insure that the setup and hold times are not being met? I am sure that will work on a slow SCLK but will definitely violate the setup and hold for a 50MHz SCLK. I think I found the issue, I downloaded the fixed version in RAM and not into the FLASH so it kept loading the old code and not the new code. thanks for your help.
  6. My timing diagram and AD5628 timing diagram both show the data is shifted out of the master on rising but into the DAC on the falling with the falling edge in the center of the bit. setup and hold from falling edge must be min 4ns each and the 50MHz clock means 10ns for each. Do you think the rising edge should be in the center of the bit?
  7. OK I am probably missing something Yes Mode 2 falling edge because the AD5628 data sheet says that the date in shifted into the DAC on the falling edge. See below the verbage and timing diagram from the data sheet and the timing diagram. You can see the setup and hold times t5 & t6 given are from the falling edge of the SCLK. From data sheet "Data from the DIN line is clocked into the 32-bit shift register on the falling edge of SCLK." and "On the 32nd falling clock edge, the last data bit is clocked in and the programmed function is executed, tha
  8. Is it mode 3? I think it’s either mode 1 or 2 because data is shifted into DAC on falling edge not rising edge. Mode 3 clock in on the rising edge, Or any I mistaken? Maybe this is the issue?
  9. I think so, But that is why I attached the bit stream that gets sent to the device on power up. Data changes from the FPGA on the rising edge to be clocked into the DAC on the Falling edge. The data stream is 32 bits hex value 080001h as indicated in the data sheet as the value needed to enable the internal reference. The 8 is the internal reference setup command and the 1 is the internal ref enable as shown in table 12 of the AD5628 data sheet. And timing is close but seems to meet the timing. but I will triple check these things when I get into work this morning. I’m thinking of ha
  10. I am interfacing to the PMOD Da4 with the ARTY4 A7. I wrote Verilog to write the internal reference register to enable the internal reference right after power up. The internal reference voltage never gets turned on. Attached is the simulation in Vivado which look just like the logic analyzer of the signals. Is there a minimum amount of time that I need to wait after power up for the reference voltage to work? My next thing I was going to try is to slow down the SCLK, but it looks like it meets all timing to me at 50MHz Or maybe I need to send a reset command on power up before se
  11. I am not sure you understand my question. I am not talking about the connector that plugs into the PMOD, but the outputs analog connector on the Pmod DA4, that outputs the 8 analog signals to the outside world since I am designing a board to plug into this connector. The schematics shows a 1 x 12 connectors yet the picture of the board shows a 2 x 6. This is all about the mechanical layout of the board and how the connectors was pinned out when the board was layed out. I attached with the two different pinouts. You can see that only pins 1 and 12 are in the same physical location on the
  12. I have chosen the PMODDA4 for my development DAC add on board and noticed that the output connector is a 2 x 6 except a female, just like the Pmod male on the Nexys A7 board but with a different pinout configuration. If you pinned those the same then you have analog output pins tied to power and ground. I am developing a filter amplifier board for the outputs of the Octal DAC and so I want to make sure that I am correct that you used a different pinout configuration between the two board. The PMODDA4 has 1,3,5,7,9,10 on one side of the connector while the PMOD male on the Nexys A& ha
  13. Here is one of the files. I just recently downloaded the AD2 software it says 2015 on the icon. The older one stopped working when I installed the new one. It was installed and used in 2014. Fig15 PWR WD EN.dwfpatterns
  14. Is the a way to convert the patterns ( .dwfpatterns files) created with the Analog Discovery 1 to be used on the Analog Discover 2?